730 lines
28 KiB
C
730 lines
28 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __FSL_ADC_H__
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#define __FSL_ADC_H__
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#include "fsl_common.h"
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/*!
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* @addtogroup lpc_adc
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* @{
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*/
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/*! @file */
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief ADC driver version 2.2.0. */
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#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
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/*@}*/
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/*!
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* @brief Flags
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*/
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enum _adc_status_flags
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{
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kADC_ThresholdCompareFlagOnChn0 = 1U << 0U, /*!< Threshold comparison event on Channel 0. */
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kADC_ThresholdCompareFlagOnChn1 = 1U << 1U, /*!< Threshold comparison event on Channel 1. */
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kADC_ThresholdCompareFlagOnChn2 = 1U << 2U, /*!< Threshold comparison event on Channel 2. */
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kADC_ThresholdCompareFlagOnChn3 = 1U << 3U, /*!< Threshold comparison event on Channel 3. */
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kADC_ThresholdCompareFlagOnChn4 = 1U << 4U, /*!< Threshold comparison event on Channel 4. */
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kADC_ThresholdCompareFlagOnChn5 = 1U << 5U, /*!< Threshold comparison event on Channel 5. */
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kADC_ThresholdCompareFlagOnChn6 = 1U << 6U, /*!< Threshold comparison event on Channel 6. */
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kADC_ThresholdCompareFlagOnChn7 = 1U << 7U, /*!< Threshold comparison event on Channel 7. */
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kADC_ThresholdCompareFlagOnChn8 = 1U << 8U, /*!< Threshold comparison event on Channel 8. */
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kADC_ThresholdCompareFlagOnChn9 = 1U << 9U, /*!< Threshold comparison event on Channel 9. */
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kADC_ThresholdCompareFlagOnChn10 = 1U << 10U, /*!< Threshold comparison event on Channel 10. */
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kADC_ThresholdCompareFlagOnChn11 = 1U << 11U, /*!< Threshold comparison event on Channel 11. */
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kADC_OverrunFlagForChn0 =
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1U << 12U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 0. */
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kADC_OverrunFlagForChn1 =
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1U << 13U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 1. */
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kADC_OverrunFlagForChn2 =
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1U << 14U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 2. */
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kADC_OverrunFlagForChn3 =
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1U << 15U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 3. */
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kADC_OverrunFlagForChn4 =
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1U << 16U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 4. */
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kADC_OverrunFlagForChn5 =
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1U << 17U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 5. */
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kADC_OverrunFlagForChn6 =
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1U << 18U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 6. */
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kADC_OverrunFlagForChn7 =
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1U << 19U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 7. */
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kADC_OverrunFlagForChn8 =
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1U << 20U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 8. */
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kADC_OverrunFlagForChn9 =
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1U << 21U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 9. */
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kADC_OverrunFlagForChn10 =
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1U << 22U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 10. */
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kADC_OverrunFlagForChn11 =
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1U << 23U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 11. */
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kADC_GlobalOverrunFlagForSeqA = 1U << 24U, /*!< Mirror the glabal OVERRUN status flag for conversion sequence A. */
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kADC_GlobalOverrunFlagForSeqB = 1U << 25U, /*!< Mirror the global OVERRUN status flag for conversion sequence B. */
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kADC_ConvSeqAInterruptFlag = 1U << 28U, /*!< Sequence A interrupt/DMA trigger. */
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kADC_ConvSeqBInterruptFlag = 1U << 29U, /*!< Sequence B interrupt/DMA trigger. */
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kADC_ThresholdCompareInterruptFlag = 1U << 30U, /*!< Threshold comparision interrupt flag. */
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kADC_OverrunInterruptFlag = 1U << 31U, /*!< Overrun interrupt flag. */
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};
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/*!
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* @brief Interrupts
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* @note Not all the interrupt options are listed here
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*/
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enum _adc_interrupt_enable
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{
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kADC_ConvSeqAInterruptEnable = ADC_INTEN_SEQA_INTEN_MASK, /*!< Enable interrupt upon completion of each individual
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conversion in sequence A, or entire sequence. */
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kADC_ConvSeqBInterruptEnable = ADC_INTEN_SEQB_INTEN_MASK, /*!< Enable interrupt upon completion of each individual
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conversion in sequence B, or entire sequence. */
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kADC_OverrunInterruptEnable = ADC_INTEN_OVR_INTEN_MASK, /*!< Enable the detection of an overrun condition on any of
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the channel data registers will cause an overrun
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interrupt/DMA trigger. */
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};
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE
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/*!
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* @brief Define selection of clock mode.
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*/
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typedef enum _adc_clock_mode
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{
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kADC_ClockSynchronousMode =
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0U, /*!< The ADC clock would be derived from the system clock based on "clockDividerNumber". */
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kADC_ClockAsynchronousMode = 1U, /*!< The ADC clock would be based on the SYSCON block's divider. */
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} adc_clock_mode_t;
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL
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/*!
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* @brief Define selection of resolution.
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*/
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typedef enum _adc_resolution
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{
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kADC_Resolution6bit = 0U, /*!< 6-bit resolution. */
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kADC_Resolution8bit = 1U, /*!< 8-bit resolution. */
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kADC_Resolution10bit = 2U, /*!< 10-bit resolution. */
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kADC_Resolution12bit = 3U, /*!< 12-bit resolution. */
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} adc_resolution_t;
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */
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#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG
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/*!
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* @brief Definfe range of the analog supply voltage VDDA.
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*/
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typedef enum _adc_voltage_range
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{
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kADC_HighVoltageRange = 0U, /* High voltage. VDD = 2.7 V to 3.6 V. */
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kADC_LowVoltageRange = 1U, /* Low voltage. VDD = 2.4 V to 2.7 V. */
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} adc_vdda_range_t;
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#endif/* FSL_FEATURE_ADC_HAS_TRIM_REG. */
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/*!
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* @brief Define selection of polarity of selected input trigger for conversion sequence.
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*/
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typedef enum _adc_trigger_polarity
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{
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kADC_TriggerPolarityNegativeEdge = 0U, /*!< A negative edge launches the conversion sequence on the trigger(s). */
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kADC_TriggerPolarityPositiveEdge = 1U, /*!< A positive edge launches the conversion sequence on the trigger(s). */
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} adc_trigger_polarity_t;
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/*!
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* @brief Define selection of conversion sequence's priority.
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*/
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typedef enum _adc_priority
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{
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kADC_PriorityLow = 0U, /*!< This sequence would be preempted when another sequence is started. */
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kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when it is started. */
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} adc_priority_t;
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/*!
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* @brief Define selection of conversion sequence's interrupt.
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*/
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typedef enum _adc_seq_interrupt_mode
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{
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kADC_InterruptForEachConversion = 0U, /*!< The sequence interrupt/DMA trigger will be set at the end of each
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individual ADC conversion inside this conversion sequence. */
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kADC_InterruptForEachSequence = 1U, /*!< The sequence interrupt/DMA trigger will be set when the entire set of
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this sequence conversions completes. */
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} adc_seq_interrupt_mode_t;
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/*!
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* @brief Define status of threshold compare result.
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*/
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typedef enum _adc_threshold_compare_status
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{
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kADC_ThresholdCompareInRange = 0U, /*!< LOW threshold <= conversion value <= HIGH threshold. */
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kADC_ThresholdCompareBelowRange = 1U, /*!< conversion value < LOW threshold. */
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kADC_ThresholdCompareAboveRange = 2U, /*!< conversion value > HIGH threshold. */
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} adc_threshold_compare_status_t;
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/*!
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* @brief Define status of threshold crossing detection result.
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*/
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typedef enum _adc_threshold_crossing_status
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{
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/* The conversion on this channel had the same relationship (above or below) to the threshold value established by
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* the designated LOW threshold value as did the previous conversion on this channel. */
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kADC_ThresholdCrossingNoDetected = 0U, /*!< No threshold Crossing detected. */
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/* Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this
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* channel was above the threshold value established by the designated LOW threshold value and the current sample is
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* below that threshold. */
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kADC_ThresholdCrossingDownward = 2U, /*!< Downward Threshold Crossing detected. */
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/* Indicates that a thre shold crossing in the upward direction has occurred - i.e. the previous sample on this
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* channel was below the threshold value established by the designated LOW threshold value and the current sample is
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* above that threshold. */
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kADC_ThresholdCrossingUpward = 3U, /*!< Upward Threshold Crossing Detected. */
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} adc_threshold_crossing_status_t;
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/*!
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* @brief Define interrupt mode for threshold compare event.
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*/
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typedef enum _adc_threshold_interrupt_mode
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{
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kADC_ThresholdInterruptDisabled = 0U, /*!< Threshold comparison interrupt is disabled. */
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kADC_ThresholdInterruptOnOutside = 1U, /*!< Threshold comparison interrupt is enabled on outside threshold. */
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kADC_ThresholdInterruptOnCrossing = 2U, /*!< Threshold comparison interrupt is enabled on crossing threshold. */
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} adc_threshold_interrupt_mode_t;
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/*!
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* @brief Define structure for configuring the block.
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*/
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typedef struct _adc_config
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{
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE
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adc_clock_mode_t clockMode; /*!< Select the clock mode for ADC converter. */
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */
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uint32_t clockDividerNumber; /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode"
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field. The divider would be plused by 1 based on the value in this field. The
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available range is in 8 bits. */
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL
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adc_resolution_t resolution; /*!< Select the conversion bits. */
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL
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bool enableBypassCalibration; /*!< By default, a calibration cycle must be performed each time the chip is
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powered-up. Re-calibration may be warranted periodically - especially if
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operating conditions have changed. To enable this option would avoid the need to
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calibrate if offset error is not a concern in the application. */
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP
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uint32_t sampleTimeNumber; /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then,
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to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE
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bool enableLowPowerMode; /*!< If disable low-power mode, ADC remains activated even when no conversions are requested.
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If enable low-power mode, The ADC is automatically powered-down when no conversions are
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taking place. */
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */
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#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG
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adc_vdda_range_t voltageRange; /*!< Configure the ADC for the appropriate operating range of the analog supply voltage VDDA.
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Failure to set the area correctly causes the ADC to return incorrect conversion results. */
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#endif/* FSL_FEATURE_ADC_HAS_TRIM_REG. */
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} adc_config_t;
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/*!
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* @brief Define structure for configuring conversion sequence.
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*/
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typedef struct _adc_conv_seq_config
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{
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uint32_t channelMask; /*!< Selects which one or more of the ADC channels will be sampled and converted when this
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sequence is launched. The masked channels would be involved in current conversion
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sequence, beginning with the lowest-order. The available range is in 12-bit. */
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uint32_t triggerMask; /*!< Selects which one or more of the available hardware trigger sources will cause this
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conversion sequence to be initiated. The available range is 6-bit.*/
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adc_trigger_polarity_t triggerPolarity; /*!< Select the trigger to lauch conversion sequence. */
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bool enableSyncBypass; /*!< To enable this feature allows the hardware trigger input to bypass synchronization
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flip-flop stages and therefore shorten the time between the trigger input signal and the
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start of a conversion. */
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bool enableSingleStep; /*!< When enabling this feature, a trigger will launch a single conversion on the next
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channel in the sequence instead of the default response of launching an entire sequence
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of conversions. */
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adc_seq_interrupt_mode_t interruptMode; /*!< Select the interrpt/DMA trigger mode. */
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} adc_conv_seq_config_t;
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/*!
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* @brief Define structure of keeping conversion result information.
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*/
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typedef struct _adc_result_info
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{
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uint32_t result; /*!< Keep the conversion data value. */
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adc_threshold_compare_status_t thresholdCompareStatus; /*!< Keep the threshold compare status. */
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adc_threshold_crossing_status_t thresholdCorssingStatus; /*!< Keep the threshold crossing status. */
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uint32_t channelNumber; /*!< Keep the channel number for this conversion. */
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bool overrunFlag; /*!< Keep the status whether the conversion is overrun or not. */
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/* The data available flag would be returned by the reading result API. */
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} adc_result_info_t;
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*******************************************************************************
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* API
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******************************************************************************/
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/*!
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* @name Initialization and Deinitialization
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* @{
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*/
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/*!
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* @brief Initialize the ADC module.
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*
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* @param base ADC peripheral base address.
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|
* @param config Pointer to configuration structure, see to #adc_config_t.
|
||
|
|
*/
|
||
|
|
void ADC_Init(ADC_Type *base, const adc_config_t *config);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Deinitialize the ADC module.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
*/
|
||
|
|
void ADC_Deinit(ADC_Type *base);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Gets an available pre-defined settings for initial configuration.
|
||
|
|
*
|
||
|
|
* This function initializes the initial configuration structure with an available settings. The default values are:
|
||
|
|
* @code
|
||
|
|
* config->clockMode = kADC_ClockSynchronousMode;
|
||
|
|
* config->clockDividerNumber = 0U;
|
||
|
|
* config->resolution = kADC_Resolution12bit;
|
||
|
|
* config->enableBypassCalibration = false;
|
||
|
|
* config->sampleTimeNumber = 0U;
|
||
|
|
* @endcode
|
||
|
|
* @param config Pointer to configuration structure.
|
||
|
|
*/
|
||
|
|
void ADC_GetDefaultConfig(adc_config_t *config);
|
||
|
|
|
||
|
|
#if !(defined(FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) && FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC)
|
||
|
|
#if defined(FSL_FEATURE_ADC_HAS_CALIB_REG) && FSL_FEATURE_ADC_HAS_CALIB_REG
|
||
|
|
/*!
|
||
|
|
* @brief Do the self hardware calibration.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @retval true Calibration succeed.
|
||
|
|
* @retval false Calibration failed.
|
||
|
|
*/
|
||
|
|
bool ADC_DoSelfCalibration(ADC_Type *base);
|
||
|
|
#else
|
||
|
|
/*!
|
||
|
|
* @brief Do the self calibration. To calibrate the ADC, set the ADC clock to 500 kHz.
|
||
|
|
* In order to achieve the specified ADC accuracy, the A/D converter must be recalibrated, at a minimum,
|
||
|
|
* following every chip reset before initiating normal ADC operation.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param frequency The ststem clock frequency to ADC.
|
||
|
|
* @retval true Calibration succeed.
|
||
|
|
* @retval false Calibration failed.
|
||
|
|
*/
|
||
|
|
bool ADC_DoSelfCalibration(ADC_Type *base, uint32_t frequency);
|
||
|
|
#endif/* FSL_FEATURE_ADC_HAS_CALIB_REG */
|
||
|
|
#endif/* FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC */
|
||
|
|
|
||
|
|
#if !(defined(FSL_FEATURE_ADC_HAS_NO_INSEL) && FSL_FEATURE_ADC_HAS_NO_INSEL)
|
||
|
|
/*!
|
||
|
|
* @brief Enable the internal temperature sensor measurement.
|
||
|
|
*
|
||
|
|
* When enabling the internal temperature sensor measurement, the channel 0 would be connected to internal sensor
|
||
|
|
* instead of external pin.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param enable Switcher to enable the feature or not.
|
||
|
|
*/
|
||
|
|
static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0x3);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* FSL_FEATURE_ADC_HAS_NO_INSEL. */
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @name Control conversion sequence A.
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enable the conversion sequence A.
|
||
|
|
*
|
||
|
|
* In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the
|
||
|
|
* sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the
|
||
|
|
* sequence during changing the sequence's setting.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param enable Switcher to enable the feature or not.
|
||
|
|
*/
|
||
|
|
static inline void ADC_EnableConvSeqA(ADC_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_SEQ_ENA_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Configure the conversion sequence A.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param config Pointer to configuration structure, see to #adc_conv_seq_config_t.
|
||
|
|
*/
|
||
|
|
void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Do trigger the sequence's conversion by software.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
*/
|
||
|
|
static inline void ADC_DoSoftwareTriggerConvSeqA(ADC_Type *base)
|
||
|
|
{
|
||
|
|
base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_START_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enable the burst conversion of sequence A.
|
||
|
|
*
|
||
|
|
* Enable the burst mode would cause the conversion sequence to be cntinuously cycled through. Other triggers would be
|
||
|
|
* ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence
|
||
|
|
* currently in process will be completed before cnversions are terminated.
|
||
|
|
* Note that a new sequence could begin just before the burst mode is disabled.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param enable Switcher to enable this feature.
|
||
|
|
*/
|
||
|
|
static inline void ADC_EnableConvSeqABurstMode(ADC_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_BURST_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_BURST_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Set the high priority for conversion sequence A.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral bass address.
|
||
|
|
*/
|
||
|
|
static inline void ADC_SetConvSeqAHighPriority(ADC_Type *base)
|
||
|
|
{
|
||
|
|
base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_LOWPRIO_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @name Control conversion sequence B.
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enable the conversion sequence B.
|
||
|
|
*
|
||
|
|
* In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the
|
||
|
|
* sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the
|
||
|
|
* sequence during changing the sequence's setting.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param enable Switcher to enable the feature or not.
|
||
|
|
*/
|
||
|
|
static inline void ADC_EnableConvSeqB(ADC_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_SEQ_ENA_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Configure the conversion sequence B.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param config Pointer to configuration structure, see to #adc_conv_seq_config_t.
|
||
|
|
*/
|
||
|
|
void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Do trigger the sequence's conversion by software.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
*/
|
||
|
|
static inline void ADC_DoSoftwareTriggerConvSeqB(ADC_Type *base)
|
||
|
|
{
|
||
|
|
base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_START_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enable the burst conversion of sequence B.
|
||
|
|
*
|
||
|
|
* Enable the burst mode would cause the conversion sequence to be continuously cycled through. Other triggers would be
|
||
|
|
* ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence
|
||
|
|
* currently in process will be completed before cnversions are terminated.
|
||
|
|
* Note that a new sequence could begin just before the burst mode is disabled.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param enable Switcher to enable this feature.
|
||
|
|
*/
|
||
|
|
static inline void ADC_EnableConvSeqBBurstMode(ADC_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_BURST_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_BURST_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Set the high priority for conversion sequence B.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral bass address.
|
||
|
|
*/
|
||
|
|
static inline void ADC_SetConvSeqBHighPriority(ADC_Type *base)
|
||
|
|
{
|
||
|
|
base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_LOWPRIO_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @name Data result.
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Get the global ADC conversion infomation of sequence A.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param info Pointer to information structure, see to #adc_result_info_t;
|
||
|
|
* @retval true The conversion result is ready.
|
||
|
|
* @retval false The conversion result is not ready yet.
|
||
|
|
*/
|
||
|
|
bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Get the global ADC conversion infomation of sequence B.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param info Pointer to information structure, see to #adc_result_info_t;
|
||
|
|
* @retval true The conversion result is ready.
|
||
|
|
* @retval false The conversion result is not ready yet.
|
||
|
|
*/
|
||
|
|
bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Get the channel's ADC conversion completed under each conversion sequence.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param channel The indicated channel number.
|
||
|
|
* @param info Pointer to information structure, see to #adc_result_info_t;
|
||
|
|
* @retval true The conversion result is ready.
|
||
|
|
* @retval false The conversion result is not ready yet.
|
||
|
|
*/
|
||
|
|
bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info);
|
||
|
|
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @name Threshold function.
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Set the threshhold pair 0 with low and high value.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param lowValue LOW threshold value.
|
||
|
|
* @param highValue HIGH threshold value.
|
||
|
|
*/
|
||
|
|
static inline void ADC_SetThresholdPair0(ADC_Type *base, uint32_t lowValue, uint32_t highValue)
|
||
|
|
{
|
||
|
|
base->THR0_LOW = ADC_THR0_LOW_THRLOW(lowValue);
|
||
|
|
base->THR0_HIGH = ADC_THR0_HIGH_THRHIGH(highValue);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Set the threshhold pair 1 with low and high value.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param lowValue LOW threshold value. The available value is with 12-bit.
|
||
|
|
* @param highValue HIGH threshold value. The available value is with 12-bit.
|
||
|
|
*/
|
||
|
|
static inline void ADC_SetThresholdPair1(ADC_Type *base, uint32_t lowValue, uint32_t highValue)
|
||
|
|
{
|
||
|
|
base->THR1_LOW = ADC_THR1_LOW_THRLOW(lowValue);
|
||
|
|
base->THR1_HIGH = ADC_THR1_HIGH_THRHIGH(highValue);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Set given channels to apply the threshold pare 0.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param channelMask Indicated channels' mask.
|
||
|
|
*/
|
||
|
|
static inline void ADC_SetChannelWithThresholdPair0(ADC_Type *base, uint32_t channelMask)
|
||
|
|
{
|
||
|
|
base->CHAN_THRSEL &= ~(channelMask);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Set given channels to apply the threshold pare 1.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param channelMask Indicated channels' mask.
|
||
|
|
*/
|
||
|
|
static inline void ADC_SetChannelWithThresholdPair1(ADC_Type *base, uint32_t channelMask)
|
||
|
|
{
|
||
|
|
base->CHAN_THRSEL |= channelMask;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @name Interrupts.
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enable interrupts for conversion sequences.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param mask Mask of interrupt mask value for global block except each channal, see to #_adc_interrupt_enable.
|
||
|
|
*/
|
||
|
|
static inline void ADC_EnableInterrupts(ADC_Type *base, uint32_t mask)
|
||
|
|
{
|
||
|
|
base->INTEN |= (0x7 & mask);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Disable interrupts for conversion sequence.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param mask Mask of interrupt mask value for global block except each channel, see to #_adc_interrupt_enable.
|
||
|
|
*/
|
||
|
|
static inline void ADC_DisableInterrupts(ADC_Type *base, uint32_t mask)
|
||
|
|
{
|
||
|
|
base->INTEN &= ~(0x7 & mask);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enable the interrupt of threshold compare event for each channel.
|
||
|
|
* @deprecated Do not use this function. It has been superceded by @ADC_EnableThresholdCompareInterrupt
|
||
|
|
*/
|
||
|
|
static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base,
|
||
|
|
uint32_t channel,
|
||
|
|
adc_threshold_interrupt_mode_t mode)
|
||
|
|
{
|
||
|
|
base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U));
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enable the interrupt of threshold compare event for each channel.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param channel Channel number.
|
||
|
|
* @param mode Interrupt mode for threshold compare event, see to #adc_threshold_interrupt_mode_t.
|
||
|
|
*/
|
||
|
|
static inline void ADC_EnableThresholdCompareInterrupt(ADC_Type *base,
|
||
|
|
uint32_t channel,
|
||
|
|
adc_threshold_interrupt_mode_t mode)
|
||
|
|
{
|
||
|
|
base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U));
|
||
|
|
}
|
||
|
|
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @name Status.
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Get status flags of ADC module.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @return Mask of status flags of module, see to #_adc_status_flags.
|
||
|
|
*/
|
||
|
|
static inline uint32_t ADC_GetStatusFlags(ADC_Type *base)
|
||
|
|
{
|
||
|
|
return base->FLAGS;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Clear status flags of ADC module.
|
||
|
|
*
|
||
|
|
* @param base ADC peripheral base address.
|
||
|
|
* @param mask Mask of status flags of module, see to #_adc_status_flags.
|
||
|
|
*/
|
||
|
|
static inline void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
|
||
|
|
{
|
||
|
|
base->FLAGS = mask; /* Write 1 to clear. */
|
||
|
|
}
|
||
|
|
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
#if defined(__cplusplus)
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
#endif /* __FSL_ADC_H__ */
|