2014-03-29 12:14:24 +08:00
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/*
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2018-10-15 01:35:07 +08:00
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* Copyright (c) 2006-2018, RT-Thread Development Team
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2014-03-29 12:14:24 +08:00
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*
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2018-10-15 01:35:07 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2014-03-29 12:14:24 +08:00
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-06 Bernard first version
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*/
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#ifndef __INTERRUPT_H__
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#define __INTERRUPT_H__
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#define INT_IRQ 0x00
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#define INT_FIQ 0x01
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#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0)
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#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10)
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#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14)
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#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40)
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#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44)
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#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48)
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#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c)
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#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50)
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#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60)
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#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64)
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#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68)
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#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c)
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#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04))
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#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20))
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#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20))
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#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20))
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#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20))
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#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20))
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#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20))
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#define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20))
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#define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20))
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#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04))
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void rt_hw_interrupt_control(int vector, int priority, int route);
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int rt_hw_interrupt_get_active(int fiq_irq);
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void rt_hw_interrupt_ack(int fiq_irq);
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void rt_hw_interrupt_trigger(int vector);
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void rt_hw_interrupt_clear(int vector);
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#endif
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