2019-01-08 11:58:09 +08:00
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/*
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2021-03-08 22:40:39 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2019-01-08 11:58:09 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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2019-01-08 18:19:11 +08:00
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* 2019-01-02 zylx first version
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* 2019-01-08 SummerGift clean up the code
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2019-01-08 11:58:09 +08:00
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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2019-01-09 10:10:39 +08:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2019-01-08 18:19:11 +08:00
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/* DMA1 stream0 */
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#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
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#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
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#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_RX_DMA_INSTANCE DMA1_Stream0
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#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn
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#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
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2019-01-08 11:58:09 +08:00
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#define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
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#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART5_RX_DMA_INSTANCE DMA1_Stream0
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#define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn
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#endif
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2019-01-08 18:19:11 +08:00
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/* DMA1 stream1 */
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#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
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2019-01-08 11:58:09 +08:00
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#define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler
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#define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART3_RX_DMA_INSTANCE DMA1_Stream1
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#define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn
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#endif
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2019-01-08 18:19:11 +08:00
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/* DMA1 stream2 */
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#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
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#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
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#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_RX_DMA_INSTANCE DMA1_Stream2
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#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn
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#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
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2019-01-08 11:58:09 +08:00
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#define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
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#define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART4_RX_DMA_INSTANCE DMA1_Stream2
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#define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn
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#endif
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2019-01-08 18:19:11 +08:00
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/* DMA1 stream3 */
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#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
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#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI2_RX_DMA_INSTANCE DMA1_Stream3
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#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn
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2019-01-08 11:58:09 +08:00
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#endif
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2019-01-08 18:19:11 +08:00
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/* DMA1 stream4 */
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#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
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#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI2_TX_DMA_INSTANCE DMA1_Stream4
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#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn
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2019-01-08 11:58:09 +08:00
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#endif
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2019-01-08 18:19:11 +08:00
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/* DMA1 stream5 */
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#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
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#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler
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#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_TX_DMA_INSTANCE DMA1_Stream5
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#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn
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#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
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2019-01-08 11:58:09 +08:00
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#define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler
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#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART2_RX_DMA_INSTANCE DMA1_Stream5
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#define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn
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#endif
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2019-01-08 18:19:11 +08:00
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/* DMA1 stream6 */
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2019-01-08 11:58:09 +08:00
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2019-01-08 18:19:11 +08:00
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/* DMA1 stream7 */
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#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
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#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
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#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_TX_DMA_INSTANCE DMA1_Stream7
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#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn
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2019-01-08 11:58:09 +08:00
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#endif
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2019-01-08 18:19:11 +08:00
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/* DMA2 stream0 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
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#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
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#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
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#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
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#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
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#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI4_RX_DMA_INSTANCE DMA2_Stream0
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#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn
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2019-01-08 11:58:09 +08:00
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#endif
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2019-01-08 18:19:11 +08:00
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/* DMA2 stream1 */
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#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
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#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
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#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI4_TX_DMA_INSTANCE DMA2_Stream1
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#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4
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#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn
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2019-01-08 11:58:09 +08:00
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#endif
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2019-01-08 18:19:11 +08:00
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/* DMA2 stream2 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
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#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
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#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
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2019-01-17 12:58:31 +08:00
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#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define UART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
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#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define UART1_RX_DMA_INSTANCE DMA2_Stream2
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#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART1_RX_DMA_IRQ DMA2_Stream2_IRQn
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2019-01-08 18:19:11 +08:00
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#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
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#define QSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler
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#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define QSPI_DMA_INSTANCE DMA2_Stream2
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#define QSPI_DMA_CHANNEL DMA_CHANNEL_11
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#define QSPI_DMA_IRQ DMA2_Stream2_IRQn
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2019-01-08 11:58:09 +08:00
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#endif
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2019-01-08 18:19:11 +08:00
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/* DMA2 stream3 */
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#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
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#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
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#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_RX_DMA_INSTANCE DMA2_Stream3
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#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2
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#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn
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#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_TX_DMA_INSTANCE DMA2_Stream3
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#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
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#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn
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#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
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#define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
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#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI4_RX_DMA_INSTANCE DMA2_Stream3
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#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_5
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#define SPI4_RX_DMA_IRQ DMA2_Stream3_IRQn
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2019-01-08 11:58:09 +08:00
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#endif
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2019-01-08 18:19:11 +08:00
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/* DMA2 stream4 */
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#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
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#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
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#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_TX_DMA_INSTANCE DMA2_Stream4
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#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2
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#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn
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#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
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#define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
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#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI4_TX_DMA_INSTANCE DMA2_Stream4
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#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5
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#define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn
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2019-01-08 11:58:09 +08:00
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#endif
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2019-01-08 18:19:11 +08:00
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/* DMA2 stream5 */
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
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#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
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#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
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2019-01-17 12:58:31 +08:00
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#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define UART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
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#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define UART1_RX_DMA_INSTANCE DMA2_Stream5
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#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART1_RX_DMA_IRQ DMA2_Stream5_IRQn
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2019-01-08 18:19:11 +08:00
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#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
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#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
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#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_RX_DMA_INSTANCE DMA2_Stream5
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#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7
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#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn
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2019-01-08 11:58:09 +08:00
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#endif
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2019-01-08 18:19:11 +08:00
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/* DMA2 stream6 */
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#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
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#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
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#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_TX_DMA_INSTANCE DMA2_Stream6
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#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7
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#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn
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2019-01-08 11:58:09 +08:00
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#endif
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2019-01-08 18:19:11 +08:00
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/* DMA2 stream7 */
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#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
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#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler
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#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define QSPI_DMA_INSTANCE DMA2_Stream7
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#define QSPI_DMA_CHANNEL DMA_CHANNEL_3
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#define QSPI_DMA_IRQ DMA2_Stream7_IRQn
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2019-01-08 11:58:09 +08:00
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#endif
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2019-01-09 10:10:39 +08:00
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#ifdef __cplusplus
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}
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#endif
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2019-01-08 11:58:09 +08:00
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#endif /* __DMA_CONFIG_H__ */
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