313 lines
8.9 KiB
C
313 lines
8.9 KiB
C
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/*
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* Copyright 2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_cdog.h"
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/*******************************************************************************
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* Definitions
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*******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.cdog"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*!
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* brief Sets the default configuration of CDOG
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*
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* This function initialize CDOG config structure to default values.
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*
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* param conf CDOG configuration structure
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*/
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void CDOG_GetDefaultConfig(cdog_config_t *conf)
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{
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/* Default configuration after reset */
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conf->lock = (uint8_t)kCDOG_LockCtrl_Unlock; /* Lock control */
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conf->timeout = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Timeout control */
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conf->miscompare = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Miscompare control */
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conf->sequence = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Sequence control */
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conf->control = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Control */
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conf->state = (uint8_t)kCDOG_FaultCtrl_NoAction; /* State control */
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conf->address = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Address control */
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conf->irq_pause = (uint8_t)kCDOG_IrqPauseCtrl_Run; /* IRQ pause control */
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conf->debug_halt = (uint8_t)kCDOG_DebugHaltCtrl_Run; /* Debug halt control */
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return;
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}
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/*!
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* brief Sets secure counter and instruction timer values
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*
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* This function sets value in RELOAD and START registers for instruction timer.
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*
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* param base CDOG peripheral base address
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* param reload reload value
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* param start start value
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*/
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void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start)
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{
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base->RELOAD = reload;
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base->START = start;
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}
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/*!
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* brief Stops secure counter and instruction timer
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*
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* This function stops instruction timer and secure counter.
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* This also change state of CDOG to IDLE.
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*
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* param base CDOG peripheral base address
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* param stop expected value which will be compared with value of secure counter
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*/
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void CDOG_Stop(CDOG_Type *base, uint32_t stop)
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{
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base->STOP = stop;
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}
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/*!
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* brief Sets secure counter and instruction timer values
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*
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* This function sets value in STOP, RELOAD and START registers
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* for instruction timer and secure counter.
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*
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* param base CDOG peripheral base address
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* param stop expected value which will be compared with value of secure counter
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* param reload reload value for instruction timer
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* param start start value for secure timer
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*/
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void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start)
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{
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base->STOP = stop;
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base->RELOAD = reload;
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base->START = start;
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}
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/*!
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* brief Add value to secure counter
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*
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* This function add specified value to secure counter.
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*
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* param base CDOG peripheral base address.
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* param add Value to be added.
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*/
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void CDOG_Add(CDOG_Type *base, uint32_t add)
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{
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base->ADD = (secure_counter_t)add;
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}
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/*!
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* brief Add 1 to secure counter
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*
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* This function add 1 to secure counter.
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*
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* param base CDOG peripheral base address.
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* param add Value to be added.
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*/
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void CDOG_Add1(CDOG_Type *base)
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{
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base->ADD1 = (secure_counter_t)0x1U;
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}
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/*!
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* brief Add 16 to secure counter
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*
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* This function add 16 to secure counter.
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*
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* param base CDOG peripheral base address.
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* param add Value to be added.
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*/
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void CDOG_Add16(CDOG_Type *base)
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{
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base->ADD16 = (secure_counter_t)0x1U;
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}
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/*!
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* brief Add 256 to secure counter
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*
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* This function add 256 to secure counter.
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*
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* param base CDOG peripheral base address.
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* param add Value to be added.
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*/
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void CDOG_Add256(CDOG_Type *base)
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{
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base->ADD256 = (secure_counter_t)0x1U;
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}
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/*!
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* brief Substract value to secure counter
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*
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* This function substract specified value to secure counter.
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*
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* param base CDOG peripheral base address.
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* param sub Value to be substracted.
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*/
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void CDOG_Sub(CDOG_Type *base, uint32_t sub)
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{
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base->SUB = (secure_counter_t)sub;
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}
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/*!
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* brief Substract 1 from secure counter
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*
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* This function substract specified 1 from secure counter.
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*
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* param base CDOG peripheral base address.
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*/
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void CDOG_Sub1(CDOG_Type *base)
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{
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base->SUB1 = (secure_counter_t)0x1U;
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}
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/*!
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* brief Substract 16 from secure counter
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*
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* This function substract specified 16 from secure counter.
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*
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* param base CDOG peripheral base address.
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*/
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void CDOG_Sub16(CDOG_Type *base)
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{
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base->SUB16 = (secure_counter_t)0x1U;
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}
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/*!
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* brief Substract 256 from secure counter
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*
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* This function substract specified 256 from secure counter.
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*
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* param base CDOG peripheral base address.
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*/
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void CDOG_Sub256(CDOG_Type *base)
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{
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base->SUB256 = (secure_counter_t)0x1U;
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}
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/*!
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* brief Checks secure counter.
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*
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* This function compares stop value with secure counter value
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* by writting to RELOAD refister.
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*
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* param base CDOG peripheral base address
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* param check expected (stop) value.
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*/
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void CDOG_Check(CDOG_Type *base, uint32_t check)
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{
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base->RESTART = check;
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}
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/*!
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* brief Set the CDOG persistent word.
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*
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* param base CDOG peripheral base address.
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* param value The value to be written.
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*/
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void CDOG_WritePersistent(CDOG_Type *base, uint32_t value)
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{
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base->PERSISTENT = value;
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}
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/*!
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* brief Get the CDOG persistent word.
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*
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* param base CDOG peripheral base address.
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* return The persistent word.
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*/
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uint32_t CDOG_ReadPersistent(CDOG_Type *base)
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{
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return base->PERSISTENT;
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}
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/*!
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* brief Initialize CDOG
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*
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* This function initializes CDOG block and setting.
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*
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* param base CDOG peripheral base address
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* param conf CDOG configuration structure
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* return Status of the init operation
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*/
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status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
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{
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/* Ungate clock to CDOG engine and reset it */
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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CLOCK_EnableClock(kCLOCK_Cdog);
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#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET)
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RESET_PeripheralReset(kCDOG_RST_SHIFT_RSTn);
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#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */
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if (base->CONTROL == 0x0U)
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{
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/* CDOG is not in IDLE mode, which may be cause after SW reset. */
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/* Writing to CONTROL register will trigger fault. */
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return kStatus_Fail;
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}
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/* Clear pending errors, otherwise the device will reset */
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/* itself immediately after enable Code Watchdog */
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if ((uint32_t)kCDOG_LockCtrl_Lock ==
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((base->CONTROL & CDOG_CONTROL_LOCK_CTRL_MASK) >> CDOG_CONTROL_LOCK_CTRL_SHIFT))
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{
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CDOG->FLAGS = CDOG_FLAGS_TO_FLAG(1U) | CDOG_FLAGS_MISCOM_FLAG(1U) | CDOG_FLAGS_SEQ_FLAG(1U) |
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CDOG_FLAGS_CNT_FLAG(1U) | CDOG_FLAGS_STATE_FLAG(1U) | CDOG_FLAGS_ADDR_FLAG(1U) |
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CDOG_FLAGS_POR_FLAG(1U);
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}
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else
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{
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CDOG->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) |
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CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) |
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CDOG_FLAGS_POR_FLAG(0U);
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}
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base->CONTROL =
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CDOG_CONTROL_TIMEOUT_CTRL(conf->timeout) | /* Action if the timeout event is triggered */
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CDOG_CONTROL_MISCOMPARE_CTRL(conf->miscompare) | /* Action if the miscompare error event is triggered */
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CDOG_CONTROL_SEQUENCE_CTRL(conf->sequence) | /* Action if the sequence error event is triggered */
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CDOG_CONTROL_CONTROL_CTRL(conf->control) | /* Action if the control error event is triggered */
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CDOG_CONTROL_STATE_CTRL(conf->state) | /* Action if the state error event is triggered */
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CDOG_CONTROL_ADDRESS_CTRL(conf->address) | /* Action if the address error event is triggered */
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CDOG_CONTROL_IRQ_PAUSE(conf->irq_pause) | /* Pause running during interrupts setup */
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CDOG_CONTROL_DEBUG_HALT_CTRL(
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conf->debug_halt) | /* Halt CDOG timer during debug so we have chance to debug code */
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CDOG_CONTROL_LOCK_CTRL(conf->lock); /* Lock control register */
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NVIC_EnableIRQ(CDOG_IRQn);
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return kStatus_Success;
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}
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/*!
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* brief Deinitialize CDOG
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*
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* This function stops CDOG secure counter.
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*
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* param base CDOG peripheral base address
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*/
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void CDOG_Deinit(CDOG_Type *base)
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{
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NVIC_DisableIRQ(CDOG_IRQn);
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#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET)
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RESET_SetPeripheralReset(kCDOG_RST_SHIFT_RSTn);
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#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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CLOCK_DisableClock(kCLOCK_Cdog);
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#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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