2020-09-04 10:52:10 +08:00
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/*
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2021-03-14 15:33:55 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2020-09-04 10:52:10 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-00-30 thread-liu first version
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*/
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#ifndef __DRV_NAND_H__
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#define __DRV_NAND_H__
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#include "board.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#define NAND_MAX_PAGE_SIZE 4096
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#define NAND_ECC_SECTOR_SIZE 512
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#define NAND_TWHR_DELAY 25
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#define NAND_TBERS_DELAY 4
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#define MT29F8G08ABACAH4 0x64A690D3 /* id */
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#define NAND_ADDR ((rt_uint32_t)0x80000000) /* nand base address */
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#define NAND_ADDR_AREA (*(__IO rt_uint8_t *)NAND_ADDR)
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#define NAND_CMD_AREA (*(__IO rt_uint8_t *)(NAND_ADDR | 1 << 16)) /* command */
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#define NAND_DATA_AREA (*(__IO rt_uint8_t *)(NAND_ADDR | 1 << 17)) /* data */
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/* nand flash command */
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#define NAND_READID 0x90
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#define NAND_FEATURE 0xEF
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#define NAND_RESET 0xFF
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#define NAND_READSTA 0x70
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#define NAND_AREA_A 0x00
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#define NAND_AREA_TRUE1 0x30
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#define NAND_WRITE0 0x80
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#define NAND_WRITE_TURE1 0x10
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#define NAND_ERASE0 0x60
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#define NAND_ERASE1 0xD0
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#define NAND_MOVEDATA_CMD0 0x00
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#define NAND_MOVEDATA_CMD1 0x35
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#define NAND_MOVEDATA_CMD2 0x85
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#define NAND_MOVEDATA_CMD3 0x10
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/* nand flash status */
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#define NAND_READY 0x40 /* read */
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#define NAND_ECC1BITERR 0x03 /* ECC 1bit err */
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#define NAND_ECC2BITERR 0x04 /* ECC 2bit or more err */
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#ifdef __cplusplus
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}
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#endif
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#endif
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