85 lines
3.2 KiB
C
85 lines
3.2 KiB
C
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-08-09 supperthomas first version
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*/
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#include "board.h"
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void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
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/** Configure the main internal regulator output voltage
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*/
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if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK)
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{
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Error_Handler();
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}
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/** Configure LSE Drive Capability
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*/
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HAL_PWR_EnableBkUpAccess();
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__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE
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|RCC_OSCILLATORTYPE_LSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 4;
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RCC_OscInitStruct.PLL.PLLN = 60;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV5;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
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{
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Error_Handler();
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}
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1
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|RCC_PERIPHCLK_I2C1|RCC_PERIPHCLK_I2C3
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|RCC_PERIPHCLK_DFSDM1|RCC_PERIPHCLK_USB
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|RCC_PERIPHCLK_SDMMC1|RCC_PERIPHCLK_ADC;
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PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
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PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
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PeriphClkInit.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1;
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PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
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PeriphClkInit.Dfsdm1ClockSelection = RCC_DFSDM1CLKSOURCE_PCLK;
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PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
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PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
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PeriphClkInit.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLLP;
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PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
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PeriphClkInit.PLLSAI1.PLLSAI1M = 5;
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PeriphClkInit.PLLSAI1.PLLSAI1N = 96;
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PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV2;
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PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV4;
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PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV4;
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PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_ADC1CLK;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
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{
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Error_Handler();
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}
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}
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