2022-09-12 19:36:11 +08:00
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/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-3-15 Wayne First version
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*
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******************************************************************************/
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#include <rtconfig.h>
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#if defined(BSP_USING_SPI)
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#define LOG_TAG "drv.spi"
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#define DBG_ENABLE
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#define DBG_SECTION_NAME LOG_TAG
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#define DBG_LEVEL DBG_INFO
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#define DBG_COLOR
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#include <rtdbg.h>
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#include <rthw.h>
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#include <rtdevice.h>
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#include <rtdef.h>
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#include <drv_spi.h>
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/* Private define ---------------------------------------------------------------*/
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#ifndef NU_SPI_USE_PDMA_MIN_THRESHOLD
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#define NU_SPI_USE_PDMA_MIN_THRESHOLD (128)
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#endif
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enum
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{
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SPI_START = -1,
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#if defined(BSP_USING_SPI0)
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SPI0_IDX,
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#endif
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#if defined(BSP_USING_SPI1)
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SPI1_IDX,
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#endif
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#if defined(BSP_USING_SPI2)
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SPI2_IDX,
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#endif
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#if defined(BSP_USING_SPI3)
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SPI3_IDX,
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#endif
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#if defined(BSP_USING_SPI4)
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SPI4_IDX,
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#endif
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#if defined(BSP_USING_SPI5)
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SPI5_IDX,
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#endif
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#if defined(BSP_USING_SPI6)
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SPI6_IDX,
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#endif
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#if defined(BSP_USING_SPI7)
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SPI7_IDX,
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#endif
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#if defined(BSP_USING_SPI8)
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SPI8_IDX,
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#endif
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#if defined(BSP_USING_SPI9)
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SPI9_IDX,
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#endif
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#if defined(BSP_USING_SPI10)
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SPI10_IDX,
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#endif
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SPI_CNT
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};
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/* Private typedef --------------------------------------------------------------*/
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/* Private functions ------------------------------------------------------------*/
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static void nu_spi_transmission_with_poll(struct nu_spi *spi_bus,
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uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word);
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static int nu_spi_register_bus(struct nu_spi *spi_bus, const char *name);
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static rt_uint32_t nu_spi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message);
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static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
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#if defined(BSP_USING_SPI_PDMA)
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static void nu_pdma_spi_rx_cb_event(void *pvUserData, uint32_t u32EventFilter);
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static rt_err_t nu_pdma_spi_rx_config(struct nu_spi *spi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word);
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static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word);
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2023-02-06 07:35:33 +08:00
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static rt_ssize_t nu_spi_pdma_transmit(struct nu_spi *spi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word);
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2022-09-12 19:36:11 +08:00
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#endif
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/* Public functions -------------------------------------------------------------*/
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void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word);
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void nu_spi_drain_rxfifo(SPI_T *spi_base);
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/* Private variables ------------------------------------------------------------*/
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static struct rt_spi_ops nu_spi_poll_ops =
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{
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.configure = nu_spi_bus_configure,
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.xfer = nu_spi_bus_xfer,
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};
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static struct nu_spi nu_spi_arr [] =
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{
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#if defined(BSP_USING_SPI0)
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{
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.name = "spi0",
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.spi_base = SPI0,
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.rstidx = SPI0_RST,
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#if defined(BSP_USING_SPI_PDMA)
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#if defined(BSP_USING_SPI0_PDMA)
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.pdma_perp_tx = PDMA_SPI0_TX,
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.pdma_perp_rx = PDMA_SPI0_RX,
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#else
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.pdma_perp_tx = NU_PDMA_UNUSED,
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.pdma_perp_rx = NU_PDMA_UNUSED,
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#endif
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#endif
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},
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#endif
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#if defined(BSP_USING_SPI1)
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{
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.name = "spi1",
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.spi_base = SPI1,
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.rstidx = SPI1_RST,
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#if defined(BSP_USING_SPI_PDMA)
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#if defined(BSP_USING_SPI1_PDMA)
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.pdma_perp_tx = PDMA_SPI1_TX,
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.pdma_perp_rx = PDMA_SPI1_RX,
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#else
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.pdma_perp_tx = NU_PDMA_UNUSED,
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.pdma_perp_rx = NU_PDMA_UNUSED,
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#endif
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#endif
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},
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#endif
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#if defined(BSP_USING_SPI2)
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{
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.name = "spi2",
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.spi_base = SPI2,
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.rstidx = SPI2_RST,
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#if defined(BSP_USING_SPI_PDMA)
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#if defined(BSP_USING_SPI2_PDMA)
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.pdma_perp_tx = PDMA_SPI2_TX,
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.pdma_perp_rx = PDMA_SPI2_RX,
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#else
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.pdma_perp_tx = NU_PDMA_UNUSED,
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.pdma_perp_rx = NU_PDMA_UNUSED,
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#endif
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#endif
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},
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#endif
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#if defined(BSP_USING_SPI3)
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{
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.name = "spi3",
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.spi_base = SPI3,
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.rstidx = SPI3_RST,
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#if defined(BSP_USING_SPI_PDMA)
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#if defined(BSP_USING_SPI3_PDMA)
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.pdma_perp_tx = PDMA_SPI3_TX,
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.pdma_perp_rx = PDMA_SPI3_RX,
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#else
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.pdma_perp_tx = NU_PDMA_UNUSED,
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.pdma_perp_rx = NU_PDMA_UNUSED,
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#endif
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#endif
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},
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#endif
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#if defined(BSP_USING_SPI4)
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{
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.name = "spi4",
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.spi_base = SPI4,
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.rstidx = SPI4_RST,
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#if defined(BSP_USING_SPI_PDMA)
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#if defined(BSP_USING_SPI4_PDMA)
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.pdma_perp_tx = PDMA_SPI4_TX,
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.pdma_perp_rx = PDMA_SPI4_RX,
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#else
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.pdma_perp_tx = NU_PDMA_UNUSED,
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.pdma_perp_rx = NU_PDMA_UNUSED,
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#endif
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#endif
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},
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#endif
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#if defined(BSP_USING_SPI5)
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{
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.name = "spi5",
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.spi_base = SPI5,
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.rstidx = SPI5_RST,
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#if defined(BSP_USING_SPI_PDMA)
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#if defined(BSP_USING_SPI5_PDMA)
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.pdma_perp_tx = PDMA_SPI5_TX,
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.pdma_perp_rx = PDMA_SPI5_RX,
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#else
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.pdma_perp_tx = NU_PDMA_UNUSED,
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.pdma_perp_rx = NU_PDMA_UNUSED,
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#endif
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#endif
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},
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#endif
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#if defined(BSP_USING_SPI6)
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{
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.name = "spi6",
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.spi_base = SPI6,
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.rstidx = SPI6_RST,
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#if defined(BSP_USING_SPI_PDMA)
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#if defined(BSP_USING_SPI6_PDMA)
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.pdma_perp_tx = PDMA_SPI6_TX,
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.pdma_perp_rx = PDMA_SPI6_RX,
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#else
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.pdma_perp_tx = NU_PDMA_UNUSED,
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.pdma_perp_rx = NU_PDMA_UNUSED,
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#endif
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#endif
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},
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#endif
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#if defined(BSP_USING_SPI7)
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{
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.name = "spi7",
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.spi_base = SPI7,
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.rstidx = SPI7_RST,
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#if defined(BSP_USING_SPI_PDMA)
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#if defined(BSP_USING_SPI7_PDMA)
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.pdma_perp_tx = PDMA_SPI7_TX,
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.pdma_perp_rx = PDMA_SPI7_RX,
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#else
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.pdma_perp_tx = NU_PDMA_UNUSED,
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.pdma_perp_rx = NU_PDMA_UNUSED,
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#endif
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#endif
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},
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#endif
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#if defined(BSP_USING_SPI8)
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{
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.name = "spi8",
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.spi_base = SPI8,
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.rstidx = SPI8_RST,
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#if defined(BSP_USING_SPI_PDMA)
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#if defined(BSP_USING_SPI8_PDMA)
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.pdma_perp_tx = PDMA_SPI8_TX,
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.pdma_perp_rx = PDMA_SPI8_RX,
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#else
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.pdma_perp_tx = NU_PDMA_UNUSED,
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.pdma_perp_rx = NU_PDMA_UNUSED,
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#endif
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#endif
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},
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#endif
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#if defined(BSP_USING_SPI9)
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{
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.name = "spi9",
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.spi_base = SPI9,
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.rstidx = SPI9_RST,
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#if defined(BSP_USING_SPI_PDMA)
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#if defined(BSP_USING_SPI9_PDMA)
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.pdma_perp_tx = PDMA_SPI9_TX,
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.pdma_perp_rx = PDMA_SPI9_RX,
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#else
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.pdma_perp_tx = NU_PDMA_UNUSED,
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.pdma_perp_rx = NU_PDMA_UNUSED,
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#endif
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#endif
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},
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#endif
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#if defined(BSP_USING_SPI10)
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{
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.name = "spi10",
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.spi_base = SPI10,
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.rstidx = SPI10_RST,
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#if defined(BSP_USING_SPI_PDMA)
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#if defined(BSP_USING_SPI10_PDMA)
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.pdma_perp_tx = PDMA_SPI10_TX,
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.pdma_perp_rx = PDMA_SPI10_RX,
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#else
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.pdma_perp_tx = NU_PDMA_UNUSED,
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.pdma_perp_rx = NU_PDMA_UNUSED,
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#endif
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#endif
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},
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#endif
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}; /* spi nu_spi */
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static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device,
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struct rt_spi_configuration *configuration)
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{
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struct nu_spi *spi_bus;
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uint32_t u32SPIMode;
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uint32_t u32BusClock;
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rt_err_t ret = RT_EOK;
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void *pvUserData;
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RT_ASSERT(device);
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RT_ASSERT(configuration);
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spi_bus = (struct nu_spi *) device->bus;
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pvUserData = device->parent.user_data;
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/* Check mode */
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switch (configuration->mode & RT_SPI_MODE_3)
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{
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case RT_SPI_MODE_0:
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u32SPIMode = SPI_MODE_0;
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break;
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case RT_SPI_MODE_1:
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u32SPIMode = SPI_MODE_1;
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break;
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case RT_SPI_MODE_2:
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|
|
u32SPIMode = SPI_MODE_2;
|
|
|
|
|
break;
|
|
|
|
|
case RT_SPI_MODE_3:
|
|
|
|
|
u32SPIMode = SPI_MODE_3;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
ret = RT_EIO;
|
|
|
|
|
goto exit_nu_spi_bus_configure;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Check data width */
|
|
|
|
|
if (!(configuration->data_width == 8 ||
|
|
|
|
|
configuration->data_width == 16 ||
|
|
|
|
|
configuration->data_width == 24 ||
|
|
|
|
|
configuration->data_width == 32))
|
|
|
|
|
{
|
|
|
|
|
ret = RT_EINVAL;
|
|
|
|
|
goto exit_nu_spi_bus_configure;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Try to set clock and get actual spi bus clock */
|
|
|
|
|
u32BusClock = SPI_SetBusClock(spi_bus->spi_base, configuration->max_hz);
|
|
|
|
|
if (configuration->max_hz > u32BusClock)
|
|
|
|
|
{
|
|
|
|
|
LOG_W("%s clock max frequency is %dHz (!= %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz);
|
|
|
|
|
configuration->max_hz = u32BusClock;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Need to initialize new configuration? */
|
|
|
|
|
if (rt_memcmp(configuration, &spi_bus->configuration, sizeof(*configuration)) != 0)
|
|
|
|
|
{
|
|
|
|
|
rt_memcpy(&spi_bus->configuration, configuration, sizeof(*configuration));
|
|
|
|
|
|
|
|
|
|
SPI_Open(spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_width, u32BusClock);
|
|
|
|
|
|
|
|
|
|
if (configuration->mode & RT_SPI_CS_HIGH)
|
|
|
|
|
{
|
|
|
|
|
/* Set CS pin to LOW */
|
|
|
|
|
if (pvUserData != RT_NULL)
|
|
|
|
|
{
|
|
|
|
|
// set to LOW */
|
|
|
|
|
rt_pin_write(*((rt_base_t *)pvUserData), PIN_LOW);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
SPI_SET_SS_LOW(spi_bus->spi_base);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* Set CS pin to HIGH */
|
|
|
|
|
if (pvUserData != RT_NULL)
|
|
|
|
|
{
|
|
|
|
|
// set to HIGH */
|
|
|
|
|
rt_pin_write(*((rt_base_t *)pvUserData), PIN_HIGH);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* Set CS pin to HIGH */
|
|
|
|
|
SPI_SET_SS_HIGH(spi_bus->spi_base);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (configuration->mode & RT_SPI_MSB)
|
|
|
|
|
{
|
|
|
|
|
/* Set sequence to MSB first */
|
|
|
|
|
SPI_SET_MSB_FIRST(spi_bus->spi_base);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* Set sequence to LSB first */
|
|
|
|
|
SPI_SET_LSB_FIRST(spi_bus->spi_base);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Clear SPI RX FIFO */
|
|
|
|
|
nu_spi_drain_rxfifo(spi_bus->spi_base);
|
|
|
|
|
|
|
|
|
|
exit_nu_spi_bus_configure:
|
|
|
|
|
|
|
|
|
|
return -(ret);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if defined(BSP_USING_SPI_PDMA)
|
|
|
|
|
static void nu_pdma_spi_rx_cb_event(void *pvUserData, uint32_t u32EventFilter)
|
|
|
|
|
{
|
|
|
|
|
rt_err_t result;
|
|
|
|
|
struct nu_spi *spi_bus = (struct nu_spi *)pvUserData;
|
|
|
|
|
|
|
|
|
|
RT_ASSERT(spi_bus);
|
|
|
|
|
|
|
|
|
|
result = rt_sem_release(spi_bus->m_psSemBus);
|
|
|
|
|
RT_ASSERT(result == RT_EOK);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void nu_pdma_spi_tx_cb_trigger(void *pvUserData, uint32_t u32UserData)
|
|
|
|
|
{
|
|
|
|
|
/* Get base address of spi register */
|
|
|
|
|
SPI_T *spi_base = (SPI_T *)pvUserData;
|
|
|
|
|
|
|
|
|
|
/* Trigger TX/RX PDMA transfer. */
|
|
|
|
|
SPI_TRIGGER_TX_RX_PDMA(spi_base);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void nu_pdma_spi_rx_cb_disable(void *pvUserData, uint32_t u32UserData)
|
|
|
|
|
{
|
|
|
|
|
/* Get base address of spi register */
|
|
|
|
|
SPI_T *spi_base = (SPI_T *)pvUserData;
|
|
|
|
|
|
|
|
|
|
/* Stop TX/RX DMA transfer. */
|
|
|
|
|
SPI_DISABLE_TX_RX_PDMA(spi_base);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static rt_err_t nu_pdma_spi_rx_config(struct nu_spi *spi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word)
|
|
|
|
|
{
|
|
|
|
|
struct nu_pdma_chn_cb sChnCB;
|
|
|
|
|
|
|
|
|
|
rt_err_t result;
|
|
|
|
|
rt_uint8_t *dst_addr = NULL;
|
|
|
|
|
nu_pdma_memctrl_t memctrl = eMemCtl_Undefined;
|
|
|
|
|
|
|
|
|
|
/* Get base address of spi register */
|
|
|
|
|
SPI_T *spi_base = spi_bus->spi_base;
|
|
|
|
|
|
|
|
|
|
rt_uint8_t spi_pdma_rx_chid = spi_bus->pdma_chanid_rx;
|
|
|
|
|
|
|
|
|
|
nu_pdma_filtering_set(spi_pdma_rx_chid, NU_PDMA_EVENT_TRANSFER_DONE);
|
|
|
|
|
|
|
|
|
|
/* Register ISR callback function */
|
|
|
|
|
sChnCB.m_eCBType = eCBType_Event;
|
|
|
|
|
sChnCB.m_pfnCBHandler = nu_pdma_spi_rx_cb_event;
|
|
|
|
|
sChnCB.m_pvUserData = (void *)spi_bus;
|
|
|
|
|
result = nu_pdma_callback_register(spi_pdma_rx_chid, &sChnCB);
|
|
|
|
|
if (result != RT_EOK)
|
|
|
|
|
{
|
|
|
|
|
goto exit_nu_pdma_spi_rx_config;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Register Disable engine dma trigger callback function */
|
|
|
|
|
sChnCB.m_eCBType = eCBType_Disable;
|
|
|
|
|
sChnCB.m_pfnCBHandler = nu_pdma_spi_rx_cb_disable;
|
|
|
|
|
sChnCB.m_pvUserData = (void *)spi_base;
|
|
|
|
|
result = nu_pdma_callback_register(spi_pdma_rx_chid, &sChnCB);
|
|
|
|
|
if (result != RT_EOK)
|
|
|
|
|
{
|
|
|
|
|
goto exit_nu_pdma_spi_rx_config;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (pu8Buf == RT_NULL)
|
|
|
|
|
{
|
|
|
|
|
memctrl = eMemCtl_SrcFix_DstFix;
|
|
|
|
|
dst_addr = (rt_uint8_t *) &spi_bus->dummy;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
memctrl = eMemCtl_SrcFix_DstInc;
|
|
|
|
|
dst_addr = pu8Buf;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
result = nu_pdma_channel_memctrl_set(spi_pdma_rx_chid, memctrl);
|
|
|
|
|
if (result != RT_EOK)
|
|
|
|
|
{
|
|
|
|
|
goto exit_nu_pdma_spi_rx_config;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
result = nu_pdma_transfer(spi_pdma_rx_chid,
|
|
|
|
|
bytes_per_word * 8,
|
|
|
|
|
(uint32_t)&spi_base->RX,
|
|
|
|
|
(uint32_t)dst_addr,
|
|
|
|
|
i32RcvLen / bytes_per_word,
|
|
|
|
|
0);
|
|
|
|
|
exit_nu_pdma_spi_rx_config:
|
|
|
|
|
|
|
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word)
|
|
|
|
|
{
|
|
|
|
|
struct nu_pdma_chn_cb sChnCB;
|
|
|
|
|
|
|
|
|
|
rt_err_t result;
|
|
|
|
|
rt_uint8_t *src_addr = NULL;
|
|
|
|
|
nu_pdma_memctrl_t memctrl = eMemCtl_Undefined;
|
|
|
|
|
|
|
|
|
|
/* Get base address of spi register */
|
|
|
|
|
SPI_T *spi_base = spi_bus->spi_base;
|
|
|
|
|
|
|
|
|
|
rt_uint8_t spi_pdma_tx_chid = spi_bus->pdma_chanid_tx;
|
|
|
|
|
|
|
|
|
|
if (pu8Buf == RT_NULL)
|
|
|
|
|
{
|
|
|
|
|
spi_bus->dummy = 0;
|
|
|
|
|
memctrl = eMemCtl_SrcFix_DstFix;
|
|
|
|
|
src_addr = (rt_uint8_t *)&spi_bus->dummy;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
memctrl = eMemCtl_SrcInc_DstFix;
|
|
|
|
|
src_addr = (rt_uint8_t *)pu8Buf;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Register Disable engine dma trigger callback function */
|
|
|
|
|
sChnCB.m_eCBType = eCBType_Trigger;
|
|
|
|
|
sChnCB.m_pfnCBHandler = nu_pdma_spi_tx_cb_trigger;
|
|
|
|
|
sChnCB.m_pvUserData = (void *)spi_base;
|
|
|
|
|
result = nu_pdma_callback_register(spi_pdma_tx_chid, &sChnCB);
|
|
|
|
|
if (result != RT_EOK)
|
|
|
|
|
{
|
|
|
|
|
goto exit_nu_pdma_spi_tx_config;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
result = nu_pdma_channel_memctrl_set(spi_pdma_tx_chid, memctrl);
|
|
|
|
|
if (result != RT_EOK)
|
|
|
|
|
{
|
|
|
|
|
goto exit_nu_pdma_spi_tx_config;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
result = nu_pdma_transfer(spi_pdma_tx_chid,
|
|
|
|
|
bytes_per_word * 8,
|
|
|
|
|
(uint32_t)src_addr,
|
|
|
|
|
(uint32_t)&spi_base->TX,
|
|
|
|
|
i32SndLen / bytes_per_word,
|
|
|
|
|
0);
|
|
|
|
|
exit_nu_pdma_spi_tx_config:
|
|
|
|
|
|
|
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* SPI PDMA transfer
|
|
|
|
|
*/
|
2023-02-06 07:35:33 +08:00
|
|
|
static rt_ssize_t nu_spi_pdma_transmit(struct nu_spi *spi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word)
|
2022-09-12 19:36:11 +08:00
|
|
|
{
|
|
|
|
|
rt_err_t result = RT_EOK;
|
|
|
|
|
|
|
|
|
|
result = nu_pdma_spi_rx_config(spi_bus, recv_addr, length, bytes_per_word);
|
|
|
|
|
RT_ASSERT(result == RT_EOK);
|
|
|
|
|
|
|
|
|
|
result = nu_pdma_spi_tx_config(spi_bus, send_addr, length, bytes_per_word);
|
|
|
|
|
RT_ASSERT(result == RT_EOK);
|
|
|
|
|
|
|
|
|
|
/* Wait RX-PDMA transfer done */
|
|
|
|
|
result = rt_sem_take(spi_bus->m_psSemBus, RT_WAITING_FOREVER);
|
|
|
|
|
RT_ASSERT(result == RT_EOK);
|
|
|
|
|
|
|
|
|
|
return length;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
rt_err_t nu_hw_spi_pdma_allocate(struct nu_spi *spi_bus)
|
|
|
|
|
{
|
|
|
|
|
/* Allocate SPI_TX nu_dma channel */
|
|
|
|
|
if ((spi_bus->pdma_chanid_tx = nu_pdma_channel_allocate(spi_bus->pdma_perp_tx)) < 0)
|
|
|
|
|
{
|
|
|
|
|
goto exit_nu_hw_spi_pdma_allocate;
|
|
|
|
|
}
|
|
|
|
|
/* Allocate SPI_RX nu_dma channel */
|
|
|
|
|
else if ((spi_bus->pdma_chanid_rx = nu_pdma_channel_allocate(spi_bus->pdma_perp_rx)) < 0)
|
|
|
|
|
{
|
|
|
|
|
nu_pdma_channel_free(spi_bus->pdma_chanid_tx);
|
|
|
|
|
goto exit_nu_hw_spi_pdma_allocate;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
spi_bus->m_psSemBus = rt_sem_create("spibus_sem", 0, RT_IPC_FLAG_FIFO);
|
|
|
|
|
RT_ASSERT(spi_bus->m_psSemBus != RT_NULL);
|
|
|
|
|
|
|
|
|
|
return RT_EOK;
|
|
|
|
|
|
|
|
|
|
exit_nu_hw_spi_pdma_allocate:
|
|
|
|
|
|
|
|
|
|
return -(RT_ERROR);
|
|
|
|
|
}
|
|
|
|
|
#endif /* #if defined(BSP_USING_SPI_PDMA) */
|
|
|
|
|
|
|
|
|
|
void nu_spi_drain_rxfifo(SPI_T *spi_base)
|
|
|
|
|
{
|
|
|
|
|
while (SPI_IS_BUSY(spi_base));
|
|
|
|
|
|
|
|
|
|
// Drain SPI RX FIFO, make sure RX FIFO is empty
|
|
|
|
|
while (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
|
|
|
|
|
{
|
|
|
|
|
SPI_ClearRxFIFO(spi_base);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int nu_spi_read(SPI_T *spi_base, uint8_t *recv_addr, uint8_t bytes_per_word)
|
|
|
|
|
{
|
|
|
|
|
int size = 0;
|
|
|
|
|
|
|
|
|
|
// Read RX data
|
|
|
|
|
if (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
|
|
|
|
|
{
|
|
|
|
|
uint32_t val;
|
|
|
|
|
// Read data from SPI RX FIFO
|
|
|
|
|
switch (bytes_per_word)
|
|
|
|
|
{
|
|
|
|
|
case 4:
|
|
|
|
|
val = SPI_READ_RX(spi_base);
|
|
|
|
|
nu_set32_le(recv_addr, val);
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
val = SPI_READ_RX(spi_base);
|
|
|
|
|
nu_set24_le(recv_addr, val);
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
val = SPI_READ_RX(spi_base);
|
|
|
|
|
nu_set16_le(recv_addr, val);
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
*recv_addr = SPI_READ_RX(spi_base);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
LOG_E("Data length is not supported.\n");
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
size = bytes_per_word;
|
|
|
|
|
}
|
|
|
|
|
return size;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int nu_spi_write(SPI_T *spi_base, const uint8_t *send_addr, uint8_t bytes_per_word)
|
|
|
|
|
{
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|
|
// Wait SPI TX send data
|
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|
while (SPI_GET_TX_FIFO_FULL_FLAG(spi_base));
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|
// Input data to SPI TX
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switch (bytes_per_word)
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|
{
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|
|
case 4:
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|
SPI_WRITE_TX(spi_base, nu_get32_le(send_addr));
|
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|
break;
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|
case 3:
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SPI_WRITE_TX(spi_base, nu_get24_le(send_addr));
|
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|
break;
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|
case 2:
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SPI_WRITE_TX(spi_base, nu_get16_le(send_addr));
|
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|
|
break;
|
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|
|
case 1:
|
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|
SPI_WRITE_TX(spi_base, *((uint8_t *)send_addr));
|
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|
|
break;
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|
|
default:
|
|
|
|
|
LOG_E("Data length is not supported.\n");
|
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|
|
|
break;
|
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|
|
|
}
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|
|
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|
|
return bytes_per_word;
|
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|
|
|
}
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|
/**
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|
* @brief SPI bus polling
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* @param dev : The pointer of the specified SPI module.
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* @param send_addr : Source address
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|
* @param recv_addr : Destination address
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|
* @param length : Data length
|
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|
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|
*/
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|
|
static void nu_spi_transmission_with_poll(struct nu_spi *spi_bus,
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|
uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word)
|
|
|
|
|
{
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|
|
SPI_T *spi_base = spi_bus->spi_base;
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|
|
// Write-only
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if ((send_addr != RT_NULL) && (recv_addr == RT_NULL))
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|
|
{
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|
|
while (length > 0)
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|
|
|
{
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|
|
send_addr += nu_spi_write(spi_base, send_addr, bytes_per_word);
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|
|
length -= bytes_per_word;
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}
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} // if (send_addr != RT_NULL && recv_addr == RT_NULL)
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// Read-only
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else if ((send_addr == RT_NULL) && (recv_addr != RT_NULL))
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|
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{
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spi_bus->dummy = 0;
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while (length > 0)
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{
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/* Input data to SPI TX FIFO */
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|
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length -= nu_spi_write(spi_base, (const uint8_t *)&spi_bus->dummy, bytes_per_word);
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/* Read data from RX FIFO */
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recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word);
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}
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} // else if (send_addr == RT_NULL && recv_addr != RT_NULL)
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// Read&Write
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else
|
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|
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{
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|
|
while (length > 0)
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|
|
{
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|
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/* Input data to SPI TX FIFO */
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|
|
send_addr += nu_spi_write(spi_base, send_addr, bytes_per_word);
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|
|
length -= bytes_per_word;
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|
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/* Read data from RX FIFO */
|
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|
|
recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word);
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|
|
|
}
|
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|
|
|
} // else
|
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|
|
|
|
|
/* Wait RX or drain RX-FIFO */
|
|
|
|
|
if (recv_addr)
|
|
|
|
|
{
|
|
|
|
|
// Wait SPI transmission done
|
|
|
|
|
while (SPI_IS_BUSY(spi_base))
|
|
|
|
|
{
|
|
|
|
|
while (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
|
|
|
|
|
{
|
|
|
|
|
recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
while (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
|
|
|
|
|
{
|
|
|
|
|
recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* Clear SPI RX FIFO */
|
|
|
|
|
nu_spi_drain_rxfifo(spi_base);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word)
|
|
|
|
|
{
|
|
|
|
|
RT_ASSERT(spi_bus != RT_NULL);
|
|
|
|
|
|
|
|
|
|
#if defined(BSP_USING_SPI_PDMA)
|
|
|
|
|
/* DMA transfer constrains */
|
|
|
|
|
if ((spi_bus->pdma_chanid_rx >= 0) &&
|
|
|
|
|
!((uint32_t)tx % bytes_per_word) &&
|
|
|
|
|
!((uint32_t)rx % bytes_per_word) &&
|
|
|
|
|
(bytes_per_word != 3) &&
|
|
|
|
|
(length >= NU_SPI_USE_PDMA_MIN_THRESHOLD))
|
|
|
|
|
nu_spi_pdma_transmit(spi_bus, tx, rx, length, bytes_per_word);
|
|
|
|
|
else
|
|
|
|
|
nu_spi_transmission_with_poll(spi_bus, tx, rx, length, bytes_per_word);
|
|
|
|
|
#else
|
|
|
|
|
nu_spi_transmission_with_poll(spi_bus, tx, rx, length, bytes_per_word);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static rt_uint32_t nu_spi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
|
|
|
|
|
{
|
|
|
|
|
struct nu_spi *spi_bus;
|
|
|
|
|
struct rt_spi_configuration *configuration;
|
|
|
|
|
uint8_t bytes_per_word;
|
|
|
|
|
void *pvUserData;
|
|
|
|
|
|
|
|
|
|
RT_ASSERT(device != RT_NULL);
|
|
|
|
|
RT_ASSERT(device->bus != RT_NULL);
|
|
|
|
|
RT_ASSERT(message != RT_NULL);
|
|
|
|
|
|
|
|
|
|
spi_bus = (struct nu_spi *) device->bus;
|
|
|
|
|
configuration = (struct rt_spi_configuration *)&spi_bus->configuration;
|
|
|
|
|
bytes_per_word = configuration->data_width / 8;
|
|
|
|
|
pvUserData = device->parent.user_data;
|
|
|
|
|
|
|
|
|
|
if ((message->length % bytes_per_word) != 0)
|
|
|
|
|
{
|
|
|
|
|
/* Say bye. */
|
|
|
|
|
LOG_E("%s: error payload length(%d%%%d != 0).\n", spi_bus->name, message->length, bytes_per_word);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (message->length > 0)
|
|
|
|
|
{
|
|
|
|
|
if (message->cs_take && !(configuration->mode & RT_SPI_NO_CS))
|
|
|
|
|
{
|
|
|
|
|
if (pvUserData != RT_NULL)
|
|
|
|
|
{
|
|
|
|
|
if (configuration->mode & RT_SPI_CS_HIGH)
|
|
|
|
|
{
|
|
|
|
|
// set to HIGH */
|
|
|
|
|
rt_pin_write(*((rt_base_t *)pvUserData), PIN_HIGH);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
// set to LOW */
|
|
|
|
|
rt_pin_write(*((rt_base_t *)pvUserData), PIN_LOW);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (configuration->mode & RT_SPI_CS_HIGH)
|
|
|
|
|
{
|
|
|
|
|
SPI_SET_SS_HIGH(spi_bus->spi_base);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
SPI_SET_SS_LOW(spi_bus->spi_base);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
nu_spi_transfer(spi_bus, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length, bytes_per_word);
|
|
|
|
|
|
|
|
|
|
if (message->cs_release && !(configuration->mode & RT_SPI_NO_CS))
|
|
|
|
|
{
|
|
|
|
|
if (pvUserData != RT_NULL)
|
|
|
|
|
{
|
|
|
|
|
if (configuration->mode & RT_SPI_CS_HIGH)
|
|
|
|
|
{
|
|
|
|
|
// set to LOW */
|
|
|
|
|
rt_pin_write(*((rt_base_t *)pvUserData), PIN_LOW);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
// set to HIGH */
|
|
|
|
|
rt_pin_write(*((rt_base_t *)pvUserData), PIN_HIGH);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (configuration->mode & RT_SPI_CS_HIGH)
|
|
|
|
|
{
|
|
|
|
|
SPI_SET_SS_LOW(spi_bus->spi_base);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
SPI_SET_SS_HIGH(spi_bus->spi_base);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return message->length;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int nu_spi_register_bus(struct nu_spi *spi_bus, const char *name)
|
|
|
|
|
{
|
|
|
|
|
return rt_spi_bus_register(&spi_bus->dev, name, &nu_spi_poll_ops);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* Hardware SPI Initial
|
|
|
|
|
*/
|
|
|
|
|
static int rt_hw_spi_init(void)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = (SPI_START + 1); i < SPI_CNT; i++)
|
|
|
|
|
{
|
|
|
|
|
SYS_ResetModule(nu_spi_arr[i].rstidx);
|
|
|
|
|
nu_spi_register_bus(&nu_spi_arr[i], nu_spi_arr[i].name);
|
|
|
|
|
#if defined(BSP_USING_SPI_PDMA)
|
|
|
|
|
nu_spi_arr[i].pdma_chanid_tx = -1;
|
|
|
|
|
nu_spi_arr[i].pdma_chanid_rx = -1;
|
|
|
|
|
if ((nu_spi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_spi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED))
|
|
|
|
|
{
|
|
|
|
|
if (nu_hw_spi_pdma_allocate(&nu_spi_arr[i]) != RT_EOK)
|
|
|
|
|
{
|
|
|
|
|
LOG_W("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_spi_arr[i].name);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
INIT_DEVICE_EXPORT(rt_hw_spi_init);
|
|
|
|
|
|
|
|
|
|
#endif //#if defined(BSP_USING_SPI)
|
