655 lines
19 KiB
C
655 lines
19 KiB
C
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/*
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* \file
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*
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* \brief SAM Direct Memory Access Controller Driver
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*
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* Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#include <string.h>
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#include "dma.h"
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#include "clock.h"
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#include "system_interrupt.h"
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struct _dma_module {
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volatile bool _dma_init;
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volatile uint32_t allocated_channels;
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uint8_t free_channels;
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};
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struct _dma_module _dma_inst = {
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._dma_init = false,
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.allocated_channels = 0,
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.free_channels = CONF_MAX_USED_CHANNEL_NUM,
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};
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/** Maximum retry counter for resuming a job transfer. */
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#define MAX_JOB_RESUME_COUNT 10000
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/** DMA channel mask. */
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#define DMA_CHANNEL_MASK (0x1f)
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COMPILER_ALIGNED(16)
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DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR;
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/** Initial write back memory section. */
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COMPILER_ALIGNED(16)
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static DmacDescriptor _write_back_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR;
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/** Internal DMA resource pool. */
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static struct dma_resource* _dma_active_resource[CONF_MAX_USED_CHANNEL_NUM];
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/* DMA channel interrup flag. */
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uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM]={0};
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/**
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* \brief Find a free channel for a DMA resource.
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*
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* Find a channel for the requested DMA resource.
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*
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* \return Status of channel allocation.
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* \retval DMA_INVALID_CHANNEL No channel available
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* \retval count Allocated channel for the DMA resource
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*/
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static uint8_t _dma_find_first_free_channel_and_allocate(void)
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{
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uint8_t count;
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uint32_t tmp;
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bool allocated = false;
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system_interrupt_enter_critical_section();
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tmp = _dma_inst.allocated_channels;
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for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
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if (!(tmp & 0x00000001)) {
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/* If free channel found, set as allocated and return
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*number */
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_dma_inst.allocated_channels |= 1 << count;
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_dma_inst.free_channels--;
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allocated = true;
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break;
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}
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tmp = tmp >> 1;
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}
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system_interrupt_leave_critical_section();
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if (!allocated) {
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return DMA_INVALID_CHANNEL;
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} else {
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return count;
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}
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}
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/**
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* \brief Release an allocated DMA channel.
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*
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* \param[in] channel Channel id to be released
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*
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*/
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static void _dma_release_channel(uint8_t channel)
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{
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_dma_inst.allocated_channels &= ~(1 << channel);
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_dma_inst.free_channels++;
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}
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/**
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* \brief Configure the DMA resource.
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*
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* \param[in] dma_resource Pointer to a DMA resource instance
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* \param[out] resource_config Configurations of the DMA resource
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*
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*/
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static void _dma_set_config(struct dma_resource *resource,
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struct dma_resource_config *resource_config)
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{
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Assert(resource);
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Assert(resource_config);
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uint32_t temp_CHCTRLB_reg;
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system_interrupt_enter_critical_section();
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/** Select the DMA channel and clear software trigger */
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DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
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DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id));
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temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
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DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \
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DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action);
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if(resource_config->event_config.input_action){
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temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT(
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resource_config->event_config.input_action);
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}
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/** Enable event output, the event output selection is configured in
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* each transfer descriptor */
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if (resource_config->event_config.event_output_enable) {
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temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE;
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}
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/* Write config to CTRLB register */
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DMAC->CHCTRLB.reg = temp_CHCTRLB_reg;
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system_interrupt_leave_critical_section();
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}
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/**
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* \brief DMA interrupt service routine.
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*
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*/
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void DMAC_Handler( void )
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{
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uint8_t active_channel;
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struct dma_resource *resource;
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uint8_t isr;
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uint32_t write_size;
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uint32_t total_size;
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system_interrupt_enter_critical_section();
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/* Get Pending channel */
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active_channel = DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk;
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Assert(_dma_active_resource[active_channel]);
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/* Get active DMA resource based on channel */
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resource = _dma_active_resource[active_channel];
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/* Select the active channel */
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DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
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isr = DMAC->CHINTFLAG.reg;
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/* Calculate block transfer size of the DMA transfer */
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total_size = descriptor_section[resource->channel_id].BTCNT.reg;
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write_size = _write_back_section[resource->channel_id].BTCNT.reg;
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resource->transfered_size = total_size - write_size;
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/* DMA channel interrupt handler */
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if (isr & DMAC_CHINTENCLR_TERR) {
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/* Clear transfer error flag */
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DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR;
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/* Set I/O ERROR status */
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resource->job_status = STATUS_ERR_IO;
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/* Execute the callback function */
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if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
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(resource->callback[DMA_CALLBACK_TRANSFER_ERROR])) {
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resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource);
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}
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} else if (isr & DMAC_CHINTENCLR_TCMPL) {
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/* Clear the transfer complete flag */
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DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL;
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/* Set job status */
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resource->job_status = STATUS_OK;
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/* Execute the callback function */
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if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
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(resource->callback[DMA_CALLBACK_TRANSFER_DONE])) {
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resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource);
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}
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} else if (isr & DMAC_CHINTENCLR_SUSP) {
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/* Clear channel suspend flag */
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DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP;
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/* Set job status */
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resource->job_status = STATUS_SUSPEND;
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/* Execute the callback function */
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if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
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(resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])){
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resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
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}
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}
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system_interrupt_leave_critical_section();
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}
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/**
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* \brief Initializes config with predefined default values.
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*
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* This function will initialize a given DMA configuration structure to
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* a set of known default values. This function should be called on
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* any new instance of the configuration structure before being
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* modified by the user application.
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*
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* The default configuration is as follows:
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* \li Software trigger is used as the transfer trigger
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* \li Priority level 0
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* \li Only software/event trigger
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* \li Requires a trigger for each transaction
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* \li No event input /output
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* \li DMA channel is disabled during sleep mode (if has the feature)
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* \param[out] config Pointer to the configuration
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*
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*/
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void dma_get_config_defaults(struct dma_resource_config *config)
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{
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Assert(config);
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/* Set as priority 0 */
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config->priority = DMA_PRIORITY_LEVEL_0;
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/* Only software/event trigger */
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config->peripheral_trigger = 0;
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/* Transaction trigger */
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config->trigger_action = DMA_TRIGGER_ACTION_TRANSACTION;
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/* Event configurations, no event input/output */
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config->event_config.input_action = DMA_EVENT_INPUT_NOACT;
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config->event_config.event_output_enable = false;
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#ifdef FEATURE_DMA_CHANNEL_STANDBY
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config->run_in_standby = false;
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#endif
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}
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/**
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* \brief Allocate a DMA with configurations.
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*
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* This function will allocate a proper channel for a DMA transfer request.
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*
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* \param[in,out] dma_resource Pointer to a DMA resource instance
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* \param[in] transfer_config Configurations of the DMA transfer
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*
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* \return Status of the allocation procedure.
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*
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* \retval STATUS_OK The DMA resource was allocated successfully
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* \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed
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*/
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enum status_code dma_allocate(struct dma_resource *resource,
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struct dma_resource_config *config)
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{
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uint8_t new_channel;
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Assert(resource);
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system_interrupt_enter_critical_section();
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if (!_dma_inst._dma_init) {
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/* Initialize clocks for DMA */
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#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
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system_ahb_clock_set_mask(MCLK_AHBMASK_DMAC);
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#else
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system_ahb_clock_set_mask(PM_AHBMASK_DMAC);
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system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB,
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PM_APBBMASK_DMAC);
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#endif
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/* Perform a software reset before enable DMA controller */
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DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
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DMAC->CTRL.reg = DMAC_CTRL_SWRST;
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/* Setup descriptor base address and write back section base
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* address */
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DMAC->BASEADDR.reg = (uint32_t)descriptor_section;
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DMAC->WRBADDR.reg = (uint32_t)_write_back_section;
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/* Enable all priority level at the same time */
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DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf);
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_dma_inst._dma_init = true;
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}
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/* Find the proper channel */
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new_channel = _dma_find_first_free_channel_and_allocate();
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/* If no channel available, return not found */
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if (new_channel == DMA_INVALID_CHANNEL) {
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system_interrupt_leave_critical_section();
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return STATUS_ERR_NOT_FOUND;
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}
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/* Set the channel */
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resource->channel_id = new_channel;
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/** Perform a reset for the allocated channel */
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DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
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DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
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DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
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#ifdef FEATURE_DMA_CHANNEL_STANDBY
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if(config->run_in_standby){
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DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
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}
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#endif
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/** Configure the DMA control,channel registers and descriptors here */
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_dma_set_config(resource, config);
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resource->descriptor = NULL;
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/* Log the DMA resource into the internal DMA resource pool */
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_dma_active_resource[resource->channel_id] = resource;
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system_interrupt_leave_critical_section();
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return STATUS_OK;
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}
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/**
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* \brief Free an allocated DMA resource.
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*
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|
|
* This function will free an allocated DMA resource.
|
||
|
|
*
|
||
|
|
* \param[in,out] resource Pointer to the DMA resource
|
||
|
|
*
|
||
|
|
* \return Status of the free procedure.
|
||
|
|
*
|
||
|
|
* \retval STATUS_OK The DMA resource was freed successfully
|
||
|
|
* \retval STATUS_BUSY The DMA resource was busy and can't be freed
|
||
|
|
* \retval STATUS_ERR_NOT_INITIALIZED DMA resource was not initialized
|
||
|
|
*/
|
||
|
|
enum status_code dma_free(struct dma_resource *resource)
|
||
|
|
{
|
||
|
|
Assert(resource);
|
||
|
|
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
|
||
|
|
|
||
|
|
system_interrupt_enter_critical_section();
|
||
|
|
|
||
|
|
/* Check if channel is busy */
|
||
|
|
if (dma_is_busy(resource)) {
|
||
|
|
system_interrupt_leave_critical_section();
|
||
|
|
return STATUS_BUSY;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check if DMA resource was not allocated */
|
||
|
|
if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) {
|
||
|
|
system_interrupt_leave_critical_section();
|
||
|
|
return STATUS_ERR_NOT_INITIALIZED;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Release the DMA resource */
|
||
|
|
_dma_release_channel(resource->channel_id);
|
||
|
|
|
||
|
|
/* Reset the item in the DMA resource pool */
|
||
|
|
_dma_active_resource[resource->channel_id] = NULL;
|
||
|
|
|
||
|
|
system_interrupt_leave_critical_section();
|
||
|
|
|
||
|
|
return STATUS_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* \brief Start a DMA transfer.
|
||
|
|
*
|
||
|
|
* This function will start a DMA transfer through an allocated DMA resource.
|
||
|
|
*
|
||
|
|
* \param[in,out] resource Pointer to the DMA resource
|
||
|
|
*
|
||
|
|
* \return Status of the transfer start procedure.
|
||
|
|
*
|
||
|
|
* \retval STATUS_OK The transfer was started successfully
|
||
|
|
* \retval STATUS_BUSY The DMA resource was busy and the transfer was not started
|
||
|
|
* \retval STATUS_ERR_INVALID_ARG Transfer size is 0 and transfer was not started
|
||
|
|
*/
|
||
|
|
enum status_code dma_start_transfer_job(struct dma_resource *resource)
|
||
|
|
{
|
||
|
|
Assert(resource);
|
||
|
|
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
|
||
|
|
|
||
|
|
system_interrupt_enter_critical_section();
|
||
|
|
|
||
|
|
/* Check if resource was busy */
|
||
|
|
if (resource->job_status == STATUS_BUSY) {
|
||
|
|
system_interrupt_leave_critical_section();
|
||
|
|
return STATUS_BUSY;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check if transfer size is valid */
|
||
|
|
if (resource->descriptor->BTCNT.reg == 0) {
|
||
|
|
system_interrupt_leave_critical_section();
|
||
|
|
return STATUS_ERR_INVALID_ARG;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Enable DMA interrupt */
|
||
|
|
system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DMA);
|
||
|
|
|
||
|
|
/* Set the interrupt flag */
|
||
|
|
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
|
||
|
|
DMAC->CHINTENSET.reg = (DMAC_CHINTENSET_MASK & g_chan_interrupt_flag[resource->channel_id]);
|
||
|
|
/* Set job status */
|
||
|
|
resource->job_status = STATUS_BUSY;
|
||
|
|
|
||
|
|
/* Set channel x descriptor 0 to the descriptor base address */
|
||
|
|
memcpy(&descriptor_section[resource->channel_id], resource->descriptor,
|
||
|
|
sizeof(DmacDescriptor));
|
||
|
|
|
||
|
|
/* Enable the transfer channel */
|
||
|
|
DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||
|
|
|
||
|
|
system_interrupt_leave_critical_section();
|
||
|
|
|
||
|
|
return STATUS_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* \brief Abort a DMA transfer.
|
||
|
|
*
|
||
|
|
* This function will abort a DMA transfer. The DMA channel used for the DMA
|
||
|
|
* resource will be disabled.
|
||
|
|
* The block transfer count will also be calculated and written to the DMA
|
||
|
|
* resource structure.
|
||
|
|
*
|
||
|
|
* \note The DMA resource will not be freed after calling this function.
|
||
|
|
* The function \ref dma_free() can be used to free an allocated resource.
|
||
|
|
*
|
||
|
|
* \param[in,out] resource Pointer to the DMA resource
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void dma_abort_job(struct dma_resource *resource)
|
||
|
|
{
|
||
|
|
uint32_t write_size;
|
||
|
|
uint32_t total_size;
|
||
|
|
|
||
|
|
Assert(resource);
|
||
|
|
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
|
||
|
|
|
||
|
|
system_interrupt_enter_critical_section();
|
||
|
|
|
||
|
|
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
|
||
|
|
DMAC->CHCTRLA.reg = 0;
|
||
|
|
|
||
|
|
system_interrupt_leave_critical_section();
|
||
|
|
|
||
|
|
/* Get transferred size */
|
||
|
|
total_size = descriptor_section[resource->channel_id].BTCNT.reg;
|
||
|
|
write_size = _write_back_section[resource->channel_id].BTCNT.reg;
|
||
|
|
resource->transfered_size = total_size - write_size;
|
||
|
|
|
||
|
|
resource->job_status = STATUS_ABORTED;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* \brief Suspend a DMA transfer.
|
||
|
|
*
|
||
|
|
* This function will request to suspend the transfer of the DMA resource.
|
||
|
|
* The channel is kept enabled, can receive transfer triggers (the transfer
|
||
|
|
* pending bit will be set), but will be removed from the arbitration scheme.
|
||
|
|
* The channel operation can be resumed by calling \ref dma_resume_job().
|
||
|
|
*
|
||
|
|
* \note This function sets the command to suspend the DMA channel
|
||
|
|
* associated with a DMA resource. The channel suspend interrupt flag
|
||
|
|
* indicates whether the transfer is truly suspended.
|
||
|
|
*
|
||
|
|
* \param[in] resource Pointer to the DMA resource
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void dma_suspend_job(struct dma_resource *resource)
|
||
|
|
{
|
||
|
|
Assert(resource);
|
||
|
|
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
|
||
|
|
|
||
|
|
system_interrupt_enter_critical_section();
|
||
|
|
|
||
|
|
/* Select the channel */
|
||
|
|
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
|
||
|
|
|
||
|
|
/* Send the suspend request */
|
||
|
|
DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_SUSPEND;
|
||
|
|
|
||
|
|
system_interrupt_leave_critical_section();
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* \brief Resume a suspended DMA transfer.
|
||
|
|
*
|
||
|
|
* This function try to resume a suspended transfer of a DMA resource.
|
||
|
|
*
|
||
|
|
* \param[in] resource Pointer to the DMA resource
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void dma_resume_job(struct dma_resource *resource)
|
||
|
|
{
|
||
|
|
uint32_t bitmap_channel;
|
||
|
|
uint32_t count = 0;
|
||
|
|
|
||
|
|
Assert(resource);
|
||
|
|
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
|
||
|
|
|
||
|
|
/* Get bitmap of the allocated DMA channel */
|
||
|
|
bitmap_channel = (1 << resource->channel_id);
|
||
|
|
|
||
|
|
/* Check if channel was suspended */
|
||
|
|
if (resource->job_status != STATUS_SUSPEND) {
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
system_interrupt_enter_critical_section();
|
||
|
|
|
||
|
|
/* Send resume request */
|
||
|
|
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
|
||
|
|
DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
|
||
|
|
|
||
|
|
system_interrupt_leave_critical_section();
|
||
|
|
|
||
|
|
/* Check if transfer job resumed */
|
||
|
|
for (count = 0; count < MAX_JOB_RESUME_COUNT; count++) {
|
||
|
|
if ((DMAC->BUSYCH.reg & bitmap_channel) == bitmap_channel) {
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (count < MAX_JOB_RESUME_COUNT) {
|
||
|
|
/* Job resumed */
|
||
|
|
resource->job_status = STATUS_BUSY;
|
||
|
|
} else {
|
||
|
|
/* Job resume timeout */
|
||
|
|
resource->job_status = STATUS_ERR_TIMEOUT;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* \brief Create a DMA transfer descriptor with configurations.
|
||
|
|
*
|
||
|
|
* This function will set the transfer configurations to the DMA transfer
|
||
|
|
* descriptor.
|
||
|
|
*
|
||
|
|
* \param[in] descriptor Pointer to the DMA transfer descriptor
|
||
|
|
* \param[in] config Pointer to the descriptor configuration structure
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void dma_descriptor_create(DmacDescriptor* descriptor,
|
||
|
|
struct dma_descriptor_config *config)
|
||
|
|
{
|
||
|
|
/* Set block transfer control */
|
||
|
|
descriptor->BTCTRL.bit.VALID = config->descriptor_valid;
|
||
|
|
descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection;
|
||
|
|
descriptor->BTCTRL.bit.BLOCKACT = config->block_action;
|
||
|
|
descriptor->BTCTRL.bit.BEATSIZE = config->beat_size;
|
||
|
|
descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable;
|
||
|
|
descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable;
|
||
|
|
descriptor->BTCTRL.bit.STEPSEL = config->step_selection;
|
||
|
|
descriptor->BTCTRL.bit.STEPSIZE = config->step_size;
|
||
|
|
|
||
|
|
/* Set transfer size, source address and destination address */
|
||
|
|
descriptor->BTCNT.reg = config->block_transfer_count;
|
||
|
|
descriptor->SRCADDR.reg = config->source_address;
|
||
|
|
descriptor->DSTADDR.reg = config->destination_address;
|
||
|
|
|
||
|
|
/* Set next transfer descriptor address */
|
||
|
|
descriptor->DESCADDR.reg = config->next_descriptor_address;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* \brief Add a DMA transfer descriptor to a DMA resource.
|
||
|
|
*
|
||
|
|
* This function will add a DMA transfer descriptor to a DMA resource.
|
||
|
|
* If there was a transfer descriptor already allocated to the DMA resource,
|
||
|
|
* the descriptor will be linked to the next descriptor address.
|
||
|
|
*
|
||
|
|
* \param[in] resource Pointer to the DMA resource
|
||
|
|
* \param[in] descriptor Pointer to the transfer descriptor
|
||
|
|
*
|
||
|
|
* \retval STATUS_OK The descriptor is added to the DMA resource
|
||
|
|
* \retval STATUS_BUSY The DMA resource was busy and the descriptor is not added
|
||
|
|
*/
|
||
|
|
enum status_code dma_add_descriptor(struct dma_resource *resource,
|
||
|
|
DmacDescriptor* descriptor)
|
||
|
|
{
|
||
|
|
DmacDescriptor* desc = resource->descriptor;
|
||
|
|
|
||
|
|
if (resource->job_status == STATUS_BUSY) {
|
||
|
|
return STATUS_BUSY;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Look up for an empty space for the descriptor */
|
||
|
|
if (desc == NULL) {
|
||
|
|
resource->descriptor = descriptor;
|
||
|
|
} else {
|
||
|
|
/* Looking for end of descriptor link */
|
||
|
|
while(desc->DESCADDR.reg != 0) {
|
||
|
|
desc = (DmacDescriptor*)(desc->DESCADDR.reg);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Set to the end of descriptor list */
|
||
|
|
desc->DESCADDR.reg = (uint32_t)descriptor;
|
||
|
|
}
|
||
|
|
|
||
|
|
return STATUS_OK;
|
||
|
|
}
|