372 lines
11 KiB
C
372 lines
11 KiB
C
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_cmp.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.cmp"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get instance number for CMP module.
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*
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* @param base CMP peripheral base address
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*/
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static uint32_t CMP_GetInstance(CMP_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to CMP bases for each instance. */
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static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to CMP clocks for each instance. */
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static const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Codes
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******************************************************************************/
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static uint32_t CMP_GetInstance(CMP_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_cmpBases); instance++)
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{
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if (s_cmpBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_cmpBases));
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return instance;
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}
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/*!
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* brief Initializes the CMP.
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*
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* This function initializes the CMP module. The operations included are as follows.
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* - Enabling the clock for CMP module.
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* - Configuring the comparator.
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* - Enabling the CMP module.
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* Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for
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* any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP.
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*
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* param base CMP peripheral base address.
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* param config Pointer to the configuration structure.
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*/
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void CMP_Init(CMP_Type *base, const cmp_config_t *config)
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{
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assert(NULL != config);
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uint8_t tmp8;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the clock. */
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CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Configure. */
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CMP_Enable(base, false); /* Disable the CMP module during configuring. */
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/* CMPx_CR1. */
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tmp8 = (uint8_t)(base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK));
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if (true == config->enableHighSpeed)
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{
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tmp8 |= CMP_CR1_PMODE_MASK;
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}
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if (true == config->enableInvertOutput)
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{
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tmp8 |= CMP_CR1_INV_MASK;
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}
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if (true == config->useUnfilteredOutput)
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{
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tmp8 |= CMP_CR1_COS_MASK;
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}
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if (true == config->enablePinOut)
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{
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tmp8 |= CMP_CR1_OPE_MASK;
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}
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#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
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if (true == config->enableTriggerMode)
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{
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tmp8 |= CMP_CR1_TRIGM_MASK;
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}
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else
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{
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tmp8 &= ~(uint8_t)CMP_CR1_TRIGM_MASK;
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}
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#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
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base->CR1 = tmp8;
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/* CMPx_CR0. */
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tmp8 = base->CR0 & ~(uint8_t)CMP_CR0_HYSTCTR_MASK;
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tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode);
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base->CR0 = tmp8;
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CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */
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}
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/*!
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* brief De-initializes the CMP module.
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*
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* This function de-initializes the CMP module. The operations included are as follows.
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* - Disabling the CMP module.
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* - Disabling the clock for CMP module.
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*
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* This function disables the clock for the CMP.
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* Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the
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* clock for the CMP, ensure that all the CMP instances are not used.
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*
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* param base CMP peripheral base address.
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*/
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void CMP_Deinit(CMP_Type *base)
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{
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/* Disable the CMP module. */
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CMP_Enable(base, false);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable the clock. */
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CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Initializes the CMP user configuration structure.
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*
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* This function initializes the user configuration structure to these default values.
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* code
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* config->enableCmp = true;
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* config->hysteresisMode = kCMP_HysteresisLevel0;
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* config->enableHighSpeed = false;
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* config->enableInvertOutput = false;
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* config->useUnfilteredOutput = false;
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* config->enablePinOut = false;
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* config->enableTriggerMode = false;
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* endcode
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* param config Pointer to the configuration structure.
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*/
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void CMP_GetDefaultConfig(cmp_config_t *config)
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{
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assert(NULL != config);
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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config->enableCmp = true; /* Enable the CMP module after initialization. */
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config->hysteresisMode = kCMP_HysteresisLevel0;
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config->enableHighSpeed = false;
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config->enableInvertOutput = false;
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config->useUnfilteredOutput = false;
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config->enablePinOut = false;
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#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
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config->enableTriggerMode = false;
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#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
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}
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/*!
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* brief Sets the input channels for the comparator.
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*
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* This function sets the input channels for the comparator.
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* Note that two input channels cannot be set the same way in the application. When the user selects the same input
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* from the analog mux to the positive and negative port, the comparator is disabled automatically.
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*
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* param base CMP peripheral base address.
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* param positiveChannel Positive side input channel number. Available range is 0-7.
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* param negativeChannel Negative side input channel number. Available range is 0-7.
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*/
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void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel)
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{
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uint8_t tmp8 = base->MUXCR;
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tmp8 &= ~(uint8_t)(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK);
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tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel);
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base->MUXCR = tmp8;
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}
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#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA
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/*!
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* brief Enables/disables the DMA request for rising/falling events.
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*
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* This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of
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* the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from
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* the CMP
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* if the DMA is disabled.
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*
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* param base CMP peripheral base address.
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* param enable Enables or disables the feature.
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*/
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void CMP_EnableDMA(CMP_Type *base, bool enable)
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{
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uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
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if (enable)
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{
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tmp8 |= CMP_SCR_DMAEN_MASK;
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}
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else
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{
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tmp8 &= ~(uint8_t)CMP_SCR_DMAEN_MASK;
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}
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base->SCR = tmp8;
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}
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#endif /* FSL_FEATURE_CMP_HAS_DMA */
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/*!
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* brief Configures the filter.
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*
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* param base CMP peripheral base address.
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* param config Pointer to the configuration structure.
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*/
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void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
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{
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assert(NULL != config);
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uint8_t tmp8;
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#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT
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/* Choose the clock source for sampling. */
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if (config->enableSample)
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{
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base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */
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}
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else
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{
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base->CR1 &= (uint8_t)(~CMP_CR1_SE_MASK); /* Choose the internal divided bus clock. */
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}
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#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
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/* Set the filter count. */
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tmp8 = (uint8_t)(base->CR0 & ~CMP_CR0_FILTER_CNT_MASK);
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tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount);
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base->CR0 = tmp8;
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/* Set the filter period. It is used as the divider to bus clock. */
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base->FPR = CMP_FPR_FILT_PER(config->filterPeriod);
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}
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/*!
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* brief Configures the internal DAC.
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*
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* param base CMP peripheral base address.
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* param config Pointer to the configuration structure. "NULL" disables the feature.
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*/
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void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config)
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{
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uint8_t tmp8 = 0U;
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if (NULL == config)
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{
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/* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/
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base->DACCR = 0U;
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return;
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}
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/* CMPx_DACCR. */
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tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */
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if (kCMP_VrefSourceVin2 == config->referenceVoltageSource)
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{
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tmp8 |= CMP_DACCR_VRSEL_MASK;
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}
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tmp8 |= CMP_DACCR_VOSEL(config->DACValue);
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base->DACCR = tmp8;
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}
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/*!
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* brief Enables the interrupts.
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*
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* param base CMP peripheral base address.
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* param mask Mask value for interrupts. See "_cmp_interrupt_enable".
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*/
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void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask)
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{
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uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
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if (0U != ((uint32_t)kCMP_OutputRisingInterruptEnable & mask))
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{
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tmp8 |= CMP_SCR_IER_MASK;
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}
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if (0U != ((uint32_t)kCMP_OutputFallingInterruptEnable & mask))
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{
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tmp8 |= CMP_SCR_IEF_MASK;
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}
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base->SCR = tmp8;
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}
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/*!
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* brief Disables the interrupts.
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*
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* param base CMP peripheral base address.
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* param mask Mask value for interrupts. See "_cmp_interrupt_enable".
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*/
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void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask)
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{
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uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
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if (0U != ((uint32_t)kCMP_OutputRisingInterruptEnable & mask))
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{
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tmp8 &= ~(uint8_t)CMP_SCR_IER_MASK;
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}
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if (0U != ((uint32_t)kCMP_OutputFallingInterruptEnable & mask))
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{
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tmp8 &= ~(uint8_t)CMP_SCR_IEF_MASK;
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}
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base->SCR = tmp8;
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}
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/*!
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* brief Gets the status flags.
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*
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* param base CMP peripheral base address.
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*
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* return Mask value for the asserted flags. See "_cmp_status_flags".
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*/
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uint32_t CMP_GetStatusFlags(CMP_Type *base)
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{
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uint32_t ret32 = 0U;
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if (0U != (CMP_SCR_CFR_MASK & base->SCR))
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{
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ret32 |= (uint32_t)kCMP_OutputRisingEventFlag;
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}
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if (0U != (CMP_SCR_CFF_MASK & base->SCR))
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{
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ret32 |= (uint32_t)kCMP_OutputFallingEventFlag;
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}
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if (0U != (CMP_SCR_COUT_MASK & base->SCR))
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{
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ret32 |= (uint32_t)kCMP_OutputAssertEventFlag;
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}
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return ret32;
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}
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/*!
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* brief Clears the status flags.
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*
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* param base CMP peripheral base address.
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* param mask Mask value for the flags. See "_cmp_status_flags".
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*/
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|
void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask)
|
||
|
|
{
|
||
|
|
uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
|
||
|
|
|
||
|
|
if (0U != ((uint32_t)kCMP_OutputRisingEventFlag & mask))
|
||
|
|
{
|
||
|
|
tmp8 |= CMP_SCR_CFR_MASK;
|
||
|
|
}
|
||
|
|
if (0U != ((uint32_t)kCMP_OutputFallingEventFlag & mask))
|
||
|
|
{
|
||
|
|
tmp8 |= CMP_SCR_CFF_MASK;
|
||
|
|
}
|
||
|
|
base->SCR = tmp8;
|
||
|
|
}
|