432 lines
14 KiB
C
432 lines
14 KiB
C
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-03-13 Liuguang the first version.
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* 2018-03-19 Liuguang add GPIO interrupt mode support.
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* 2018-11-30 yangjie The first version for LPC54114
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* 2019-07-20 Magicoe The first version for LPC55S6x
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*/
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#include "drv_pin.h"
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#include "fsl_common.h"
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#include "fsl_iocon.h"
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#include "fsl_gpio.h"
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#include "fsl_gint.h"
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#include "fsl_pint.h"
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#include "fsl_inputmux.h"
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#ifdef RT_USING_PIN
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#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
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#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
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#endif
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#define get_port(x) ((x-1) / 32)
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#define get_pin(x) ((x-1) % 32)
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#define PIN_MAX_VAL 64
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#define IRQ_MAX_VAL 8
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struct lpc_pin
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{
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rt_uint16_t pin;
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GPIO_Type *gpio;
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rt_uint8_t gpio_port;
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rt_uint32_t gpio_pin;
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};
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#define __ARRAY_LEN(array) (sizeof(array)/sizeof(array[0]))
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#define __LPC55S69_PIN_DEFAULT {0, 0, 0, 0}
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#define __LPC55S69_PIN(INDEX, REG, PORT, PIN) {INDEX, REG, PORT, PIN}
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static struct rt_pin_ops lpc_pin_ops;
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static struct lpc_pin lpc_pin_map[] =
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{
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__LPC55S69_PIN_DEFAULT,
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/* PIO0 / GPIO0 */
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__LPC55S69_PIN( 1, GPIO, 0, 0), /* PIO0_00 */
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__LPC55S69_PIN( 2, GPIO, 0, 1), /* PIO0_01 */
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__LPC55S69_PIN( 3, GPIO, 0, 2), /* PIO0_02 */
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__LPC55S69_PIN( 4, GPIO, 0, 3), /* PIO0_04 */
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__LPC55S69_PIN( 5, GPIO, 0, 4), /* PIO0_04 */
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__LPC55S69_PIN( 6, GPIO, 0, 5), /* PIO0_05 */
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__LPC55S69_PIN( 7, GPIO, 0, 6), /* PIO0_06 */
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__LPC55S69_PIN( 8, GPIO, 0, 7), /* PIO0_07 */
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__LPC55S69_PIN( 9, GPIO, 0, 8), /* PIO0_08 */
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__LPC55S69_PIN(10, GPIO, 0, 9), /* PIO0_09 */
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__LPC55S69_PIN(11, GPIO, 0, 10), /* PIO0_10 */
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__LPC55S69_PIN(12, GPIO, 0, 11), /* PIO0_11 */
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__LPC55S69_PIN(13, GPIO, 0, 12), /* PIO0_12 */
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__LPC55S69_PIN(14, GPIO, 0, 13), /* PIO0_13 */
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__LPC55S69_PIN(15, GPIO, 0, 14), /* PIO0_14 */
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__LPC55S69_PIN(16, GPIO, 0, 15), /* PIO0_15 */
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__LPC55S69_PIN(17, GPIO, 0, 16), /* PIO0_16 */
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__LPC55S69_PIN(18, GPIO, 0, 17), /* PIO0_17 */
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__LPC55S69_PIN(19, GPIO, 0, 18), /* PIO0_18 */
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__LPC55S69_PIN(20, GPIO, 0, 19), /* PIO0_19 */
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__LPC55S69_PIN(21, GPIO, 0, 20), /* PIO0_20 */
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__LPC55S69_PIN(22, GPIO, 0, 21), /* PIO0_21 */
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__LPC55S69_PIN(23, GPIO, 0, 22), /* PIO0_22 */
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__LPC55S69_PIN(24, GPIO, 0, 23), /* PIO0_23 */
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__LPC55S69_PIN(25, GPIO, 0, 24), /* PIO0_24 */
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__LPC55S69_PIN(26, GPIO, 0, 25), /* PIO0_25 */
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__LPC55S69_PIN(27, GPIO, 0, 26), /* PIO0_26 */
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__LPC55S69_PIN(28, GPIO, 0, 27), /* PIO0_27 */
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__LPC55S69_PIN(29, GPIO, 0, 28), /* PIO0_28 */
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__LPC55S69_PIN(30, GPIO, 0, 29), /* PIO0_29 */
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__LPC55S69_PIN(31, GPIO, 0, 30), /* PIO0_30 */
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__LPC55S69_PIN(32, GPIO, 0, 31), /* PIO0_31 */
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/* PIO1 / GPIO, 1 */
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__LPC55S69_PIN(33, GPIO, 1, 0), /* PIO1_00 */
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__LPC55S69_PIN(34, GPIO, 1, 1), /* PIO1_01 */
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__LPC55S69_PIN(35, GPIO, 1, 2), /* PIO1_02 */
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__LPC55S69_PIN(36, GPIO, 1, 3), /* PIO1_03 */
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__LPC55S69_PIN(37, GPIO, 1, 4), /* PIO1_04 */
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__LPC55S69_PIN(38, GPIO, 1, 5), /* PIO1_05 */
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__LPC55S69_PIN(39, GPIO, 1, 6), /* PIO1_06 */
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__LPC55S69_PIN(40, GPIO, 1, 7), /* PIO1_07 */
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__LPC55S69_PIN(41, GPIO, 1, 8), /* PIO1_08 */
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__LPC55S69_PIN(42, GPIO, 1, 9), /* PIO1_09 */
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__LPC55S69_PIN(43, GPIO, 1, 10), /* PIO1_10 */
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__LPC55S69_PIN(44, GPIO, 1, 11), /* PIO1_11 */
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__LPC55S69_PIN(45, GPIO, 1, 12), /* PIO1_12 */
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__LPC55S69_PIN(46, GPIO, 1, 13), /* PIO1_13 */
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__LPC55S69_PIN(47, GPIO, 1, 14), /* PIO1_14 */
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__LPC55S69_PIN(48, GPIO, 1, 15), /* PIO1_15 */
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__LPC55S69_PIN(49, GPIO, 1, 16), /* PIO1_16 */
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__LPC55S69_PIN(50, GPIO, 1, 17), /* PIO1_17 */
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__LPC55S69_PIN(51, GPIO, 1, 18), /* PIO1_18 */
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__LPC55S69_PIN(52, GPIO, 1, 19), /* PIO1_19 */
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__LPC55S69_PIN(53, GPIO, 1, 20), /* PIO1_20 */
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__LPC55S69_PIN(54, GPIO, 1, 21), /* PIO1_21 */
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__LPC55S69_PIN(55, GPIO, 1, 22), /* PIO1_22 */
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__LPC55S69_PIN(56, GPIO, 1, 23), /* PIO1_23 */
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__LPC55S69_PIN(57, GPIO, 1, 24), /* PIO1_24 */
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__LPC55S69_PIN(58, GPIO, 1, 25), /* PIO1_25 */
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__LPC55S69_PIN(59, GPIO, 1, 26), /* PIO1_26 */
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__LPC55S69_PIN(60, GPIO, 1, 27), /* PIO1_27 */
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__LPC55S69_PIN(61, GPIO, 1, 28), /* PIO1_28 */
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__LPC55S69_PIN(62, GPIO, 1, 29), /* PIO1_29 */
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__LPC55S69_PIN(63, GPIO, 1, 30), /* PIO1_30 */
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__LPC55S69_PIN(64, GPIO, 1, 31), /* PIO1_31 */
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};
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struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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int dir;
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uint32_t pin_cfg;
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if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0))
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{
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return;
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}
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switch (mode)
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{
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case PIN_MODE_OUTPUT:
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{
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dir = kGPIO_DigitalOutput;
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pin_cfg = IOCON_FUNC0 | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP;
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}
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break;
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case PIN_MODE_INPUT:
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{
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dir = kGPIO_DigitalInput;
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pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN;
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}
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break;
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case PIN_MODE_INPUT_PULLDOWN:
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{
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dir = kGPIO_DigitalInput;
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pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLDOWN;
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}
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break;
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case PIN_MODE_INPUT_PULLUP:
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{
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dir = kGPIO_DigitalInput;
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pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP;
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}
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break;
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case PIN_MODE_OUTPUT_OD:
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{
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dir = kGPIO_DigitalOutput;
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pin_cfg = IOCON_FUNC0 | IOCON_OPENDRAIN_EN | IOCON_DIGITAL_EN;
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}
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break;
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}
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/* Enable IOCON Clock */
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CLOCK_EnableClock(kCLOCK_Iocon);
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IOCON->PIO[lpc_pin_map[pin].gpio_port][lpc_pin_map[pin].gpio_pin] = pin_cfg;
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/* Disable IOCON Clock -- To Save Power */
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CLOCK_DisableClock(kCLOCK_Iocon);
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gpio_pin_config_t pin_config = {(gpio_pin_direction_t)dir, 1};
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GPIO_PinInit(GPIO, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, &pin_config);
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}
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static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0))
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{
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return;
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}
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GPIO_PinWrite(lpc_pin_map[pin].gpio, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, value);
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}
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static int lpc_pin_read(rt_device_t dev, rt_base_t pin)
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{
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int value;
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if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0))
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{
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return RT_ERROR;
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}
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value = GPIO_PinRead(lpc_pin_map[pin].gpio, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin);
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return value;
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}
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static void pin_irq_hdr(pint_pin_int_t pintr, uint32_t pmatch_status)
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{
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int irqno = 0;
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for(irqno = 0; irqno < IRQ_MAX_VAL; irqno ++)
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{
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if((irqno) == pintr)
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{
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break;
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}
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}
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if(irqno >= IRQ_MAX_VAL)
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return;
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if (pin_irq_hdr_tab[irqno].hdr)
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{
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pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
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}
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}
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void callback(pint_pin_int_t pintr, uint32_t pmatch_status)
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{
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pin_irq_hdr(pintr, pmatch_status);
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}
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/* IRQ handler functions overloading weak symbols in the startup */
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void PIN_INT0_IRQHandler(void)
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{
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uint32_t pmstatus;
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/* Reset pattern match detection */
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pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
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pin_irq_hdr(kPINT_PinInt0, pmstatus);
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if ((PINT->ISEL & 0x1U) == 0x0U)
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{
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/* Edge sensitive: clear Pin interrupt after callback */
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PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0);
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}
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}
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static rt_err_t lpc_pin_attach_irq(struct rt_device *device,
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rt_int32_t pin,
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rt_uint32_t mode,
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void (*hdr)(void *args),
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void *args)
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{
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int trigger_mode, pin_initx, pintsel, pin_cfg, i;
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if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0))
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{
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return RT_ERROR;
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}
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switch (mode)
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{
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case PIN_IRQ_MODE_RISING:
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trigger_mode = kPINT_PinIntEnableRiseEdge;
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break;
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case PIN_IRQ_MODE_FALLING:
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trigger_mode = kPINT_PinIntEnableFallEdge;
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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trigger_mode = kPINT_PinIntEnableBothEdges;
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break;
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case PIN_IRQ_MODE_HIGH_LEVEL:
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trigger_mode = kPINT_PinIntEnableHighLevel;
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break;
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case PIN_IRQ_MODE_LOW_LEVEL:
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trigger_mode = kPINT_PinIntEnableLowLevel;
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break;
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}
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/* Get inputmux_connection_t */
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pintsel = (pin - 1 + (0xC0U << 20));
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for(i = 0; i < IRQ_MAX_VAL; i++)
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{
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if(pin_irq_hdr_tab[i].pin == -1)
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{
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pin_initx = kPINT_PinInt0 + i;
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pin_irq_hdr_tab[i].pin = pin;
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pin_irq_hdr_tab[i].mode = trigger_mode;
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pin_irq_hdr_tab[i].hdr = hdr;
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pin_irq_hdr_tab[i].args = args;
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break;
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}
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}
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if(i >= IRQ_MAX_VAL)
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return RT_ERROR;
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/* Initialize PINT */
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PINT_Init(PINT);
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/* Enable Input and IOCon clk */
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/* AttachSignal */
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/* Connect trigger sources to PINT */
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INPUTMUX_Init(INPUTMUX);
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INPUTMUX_AttachSignal(INPUTMUX, i, (inputmux_connection_t)pintsel);
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/* Turnoff clock to inputmux to save power. Clock is only needed to make changes */
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INPUTMUX_Deinit(INPUTMUX);
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pin_cfg = ((IOCON->PIO[lpc_pin_map[pin].gpio_port][lpc_pin_map[pin].gpio_pin] &
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(~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_FILTEROFF_MASK))) /* Mask bits to zero which are setting */
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| IOCON_PIO_FUNC(0) /* Selects pin function.: PORT18 (pin 28) is configured as PIO1_8 */
|
||
|
|
| IOCON_PIO_DIGIMODE(1) /* Select Analog/Digital mode.: Digital mode. */
|
||
|
|
| IOCON_PIO_FILTEROFF(0)); /* Controls input glitch filter.: Filter enabled. Noise pulses below approximately 10 ns are filtered out. */
|
||
|
|
|
||
|
|
IOCON_PinMuxSet(IOCON, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, pin_cfg);
|
||
|
|
|
||
|
|
/* PINT_PinInterruptConfig */
|
||
|
|
PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback);
|
||
|
|
/* Enable callbacks for PINTx by Index */
|
||
|
|
PINT_EnableCallbackByIndex(PINT, (pint_pin_int_t)pin_initx);
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0))
|
||
|
|
{
|
||
|
|
return RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
for(i = 0; i < IRQ_MAX_VAL; i++)
|
||
|
|
{
|
||
|
|
if(pin_irq_hdr_tab[i].pin == pin)
|
||
|
|
{
|
||
|
|
pin_irq_hdr_tab[i].pin = -1;
|
||
|
|
pin_irq_hdr_tab[i].hdr = RT_NULL;
|
||
|
|
pin_irq_hdr_tab[i].mode = 0;
|
||
|
|
pin_irq_hdr_tab[i].args = RT_NULL;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
|
||
|
|
{
|
||
|
|
int irqn_type, i;
|
||
|
|
|
||
|
|
if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0))
|
||
|
|
{
|
||
|
|
return RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
for(i = 0; i < IRQ_MAX_VAL; i++)
|
||
|
|
{
|
||
|
|
if(pin_irq_hdr_tab[i].pin == pin)
|
||
|
|
{
|
||
|
|
switch(i)
|
||
|
|
{
|
||
|
|
case 0: irqn_type = PIN_INT0_IRQn; break;
|
||
|
|
case 1: irqn_type = PIN_INT1_IRQn; break;
|
||
|
|
case 2: irqn_type = PIN_INT2_IRQn; break;
|
||
|
|
case 3: irqn_type = PIN_INT3_IRQn; break;
|
||
|
|
case 4: irqn_type = PIN_INT4_IRQn; break;
|
||
|
|
case 5: irqn_type = PIN_INT5_IRQn; break;
|
||
|
|
case 6: irqn_type = PIN_INT6_IRQn; break;
|
||
|
|
case 7: irqn_type = PIN_INT7_IRQn; break;
|
||
|
|
default:break;
|
||
|
|
}
|
||
|
|
if(enabled)
|
||
|
|
{
|
||
|
|
/* PINT_EnableCallback */
|
||
|
|
PINT_PinInterruptClrStatusAll(PINT);
|
||
|
|
NVIC_ClearPendingIRQ((IRQn_Type)irqn_type);
|
||
|
|
PINT_PinInterruptClrStatus(PINT, (pint_pin_int_t)(kPINT_PinInt0 + i));
|
||
|
|
EnableIRQ((IRQn_Type)irqn_type);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* PINT_DisableCallback */
|
||
|
|
DisableIRQ((IRQn_Type)irqn_type);
|
||
|
|
PINT_PinInterruptClrStatus(PINT, (pint_pin_int_t)(kPINT_PinInt0 + i));
|
||
|
|
NVIC_ClearPendingIRQ((IRQn_Type)irqn_type);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if(i >= IRQ_MAX_VAL)
|
||
|
|
return RT_ERROR;
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
int rt_hw_pin_init(void)
|
||
|
|
{
|
||
|
|
int ret = RT_EOK;
|
||
|
|
|
||
|
|
lpc_pin_ops.pin_mode = lpc_pin_mode;
|
||
|
|
lpc_pin_ops.pin_read = lpc_pin_read;
|
||
|
|
lpc_pin_ops.pin_write = lpc_pin_write;
|
||
|
|
lpc_pin_ops.pin_attach_irq = lpc_pin_attach_irq;
|
||
|
|
lpc_pin_ops.pin_detach_irq = lpc_pin_detach_irq;
|
||
|
|
lpc_pin_ops.pin_irq_enable = lpc_pin_irq_enable;
|
||
|
|
|
||
|
|
ret = rt_device_pin_register("pin", &lpc_pin_ops, RT_NULL);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
INIT_BOARD_EXPORT(rt_hw_pin_init);
|
||
|
|
|
||
|
|
#endif /*RT_USING_PIN */
|
||
|
|
|
||
|
|
// end file
|