671 lines
18 KiB
C
671 lines
18 KiB
C
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-06-30 thread-liu first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <board.h>
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#ifdef BSP_USING_NAND
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#define DRV_DEBUG
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#define LOG_TAG "drv.nand"
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#include <drv_log.h>
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#include "drv_nand.h"
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#define NAND_RB_PIN GET_PIN(D, 6)
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static rt_uint32_t ecc_rdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE];
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static rt_uint32_t ecc_hdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE];
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struct rthw_fmc
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{
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rt_uint32_t id;
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struct rt_mutex lock;
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};
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static struct rthw_fmc _device = {0};
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static void rt_hw_nand_gpio_init(void)
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{
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GPIO_InitTypeDef GPIO_InitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
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if (IS_ENGINEERING_BOOT_MODE())
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{
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FMC;
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PeriphClkInit.AdcClockSelection = RCC_FMCCLKSOURCE_ACLK;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
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{
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Error_Handler();
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}
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}
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__HAL_RCC_FMC_CLK_ENABLE();
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__HAL_RCC_GPIOD_CLK_ENABLE();
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__HAL_RCC_GPIOE_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_ENABLE();
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/* PD6 R/B */
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GPIO_InitStruct.Pin = GPIO_PIN_6;
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GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
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/* PG9 NCE */
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GPIO_InitStruct.Pin = GPIO_PIN_9;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
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HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
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/* PD0,1,4,5,11,12,14,15 */
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GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 |
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GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_14 | GPIO_PIN_15;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
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/* PE7,8,9,10 */
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GPIO_InitStruct.Pin = GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10;
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HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
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}
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/* nand delay */
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static void rt_hw_nand_delay(volatile uint32_t i)
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{
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while (i > 0)
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{
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i--;
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}
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}
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/* read nand flash status */
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static rt_err_t rt_hw_nand_read_status(void)
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{
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rt_err_t result = RT_EOK;
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NAND_CMD_AREA = NAND_READSTA;
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rt_hw_nand_delay(NAND_TWHR_DELAY);
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result = NAND_ADDR_AREA;
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return result;
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}
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/* wait nand flash read */
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static rt_err_t rt_hw_nand_wait_ready(void)
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{
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rt_err_t result = RT_EOK;
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static uint32_t time = 0;
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while (1)
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{
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result = rt_hw_nand_read_status();
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if (result & NAND_READY)
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{
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break;
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}
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time++;
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if (time >= 0X1FFFFFFF)
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{
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return RT_ETIMEOUT;
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}
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}
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return RT_EOK;
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}
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/* set nand mode */
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static rt_err_t rt_hw_nand_set_mode(uint8_t mode)
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{
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NAND_CMD_AREA = NAND_FEATURE;
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NAND_DATA_AREA = 0x01;
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NAND_ADDR_AREA = mode;
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NAND_ADDR_AREA = 0;
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NAND_ADDR_AREA = 0;
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NAND_ADDR_AREA = 0;
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if (rt_hw_nand_wait_ready() == RT_EOK)
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{
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return RT_EOK;
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}
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else
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{
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return RT_ERROR;
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}
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}
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/* reset nand flash */
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static rt_err_t rt_hw_nand_reset(void)
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{
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NAND_CMD_AREA = NAND_RESET;
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if (rt_hw_nand_wait_ready() == RT_EOK)
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{
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return RT_EOK; /* success */
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}
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else
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{
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return RT_ERROR;
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}
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}
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/* read nand flash id */
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static rt_err_t _read_id(struct rt_mtd_nand_device *device)
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{
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RT_ASSERT(device != RT_NULL);
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uint8_t deviceid[5];
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NAND_CMD_AREA = NAND_READID; /* read id command */
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NAND_DATA_AREA = 0x00;
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deviceid[0] = NAND_ADDR_AREA; /* Byte 0 */
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deviceid[1] = NAND_ADDR_AREA; /* Byte 1 */
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deviceid[2] = NAND_ADDR_AREA; /* Byte 2 */
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deviceid[3] = NAND_ADDR_AREA; /* Byte 3 */
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deviceid[4] = NAND_ADDR_AREA; /* Byte 4 */
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_device.id = ((uint32_t)deviceid[4]) << 24 | ((uint32_t)deviceid[3]) << 16 | ((uint32_t)deviceid[2]) << 8 | deviceid[1];
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LOG_D("nand id: 0x%08x", _device.id);
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return RT_EOK;
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}
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static rt_uint8_t rt_hw_nand_ecc_check(rt_uint32_t generatedEcc, rt_uint32_t readEcc, rt_uint8_t* data)
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{
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#define ECC_MASK28 0x0FFFFFFF /* 28 valid ECC parity bits. */
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#define ECC_MASK 0x05555555 /* 14 ECC parity bits. */
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rt_uint32_t count, bitNum, byteAddr;
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rt_uint32_t mask;
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rt_uint32_t syndrome;
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rt_uint32_t eccP; /* 14 even ECC parity bits. */
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rt_uint32_t eccPn; /* 14 odd ECC parity bits. */
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syndrome = (generatedEcc ^ readEcc) & ECC_MASK28;
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if (syndrome == 0)
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{
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return (RT_EOK); /* No errors in data. */
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}
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eccPn = syndrome & ECC_MASK; /* Get 14 odd parity bits. */
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eccP = (syndrome >> 1) & ECC_MASK; /* Get 14 even parity bits. */
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if ((eccPn ^ eccP) == ECC_MASK) /* 1-bit correctable error ? */
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{
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bitNum = (eccP & 0x01) |
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((eccP >> 1) & 0x02) |
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((eccP >> 2) & 0x04);
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LOG_D("ECC bit %d\n",bitNum);
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byteAddr = ((eccP >> 6) & 0x001) |
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((eccP >> 7) & 0x002) |
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((eccP >> 8) & 0x004) |
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((eccP >> 9) & 0x008) |
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((eccP >> 10) & 0x010) |
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((eccP >> 11) & 0x020) |
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((eccP >> 12) & 0x040) |
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((eccP >> 13) & 0x080) |
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((eccP >> 14) & 0x100) |
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((eccP >> 15) & 0x200) |
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((eccP >> 16) & 0x400) ;
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data[ byteAddr ] ^= 1 << bitNum;
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return RT_EOK;
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}
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/* Count number of one's in the syndrome. */
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count = 0;
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mask = 0x00800000;
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while (mask)
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{
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if (syndrome & mask)
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count++;
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mask >>= 1;
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}
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if (count == 1) /* Error in the ECC itself. */
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return RT_EIO;
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return RT_EIO; /* Unable to correct data. */
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#undef ECC_MASK
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#undef ECC_MASK24
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}
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static rt_err_t _read_page(struct rt_mtd_nand_device *device,
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rt_off_t page,
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rt_uint8_t *data,
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rt_uint32_t data_len,
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rt_uint8_t *spare,
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rt_uint32_t spare_len)
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{
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RT_ASSERT(device != RT_NULL);
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rt_uint32_t index, i, tickstart, eccnum;
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rt_err_t result;
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rt_uint8_t *p = RT_NULL;
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page = page + device->block_start * device->pages_per_block;
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if (page / device->pages_per_block > device->block_end)
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{
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return -RT_EIO;
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}
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rt_mutex_take(&_device.lock, RT_WAITING_FOREVER);
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if (data && data_len)
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{
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NAND_CMD_AREA = NAND_AREA_A;
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NAND_DATA_AREA = (rt_uint8_t)0;
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NAND_DATA_AREA = (rt_uint8_t)(0 >> 8);
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NAND_DATA_AREA = (rt_uint8_t)page;
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NAND_DATA_AREA = (rt_uint8_t)(page >> 8);
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NAND_DATA_AREA = (rt_uint8_t)(page >> 16);
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NAND_CMD_AREA = NAND_AREA_TRUE1;
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rt_hw_nand_delay(10);
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/* not an integer multiple of NAND ECC SECTOR SIZE, no ECC checks*/
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if (data_len % NAND_ECC_SECTOR_SIZE)
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{
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for (i = 0; i < data_len; i++)
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{
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*data++ = NAND_ADDR_AREA;
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}
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}
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else
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{
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eccnum = data_len/NAND_ECC_SECTOR_SIZE;
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p = data;
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for (index = 0; index < 4; index++)
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{
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FMC_Bank3_R->PCR |= 1<<6; /* enable ecc */
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for (i = 0; i < NAND_ECC_SECTOR_SIZE; i++)
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{
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*data++ = NAND_ADDR_AREA;
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}
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/* Get tick */
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tickstart = rt_tick_get();
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/* Wait until FIFO is empty */
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while ((FMC_Bank3_R->SR & (1 << 6)) == RESET)
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{
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/* Check for the Timeout */
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if ((rt_tick_get() - tickstart) > 10000)
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{
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result = RT_ETIMEOUT;
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goto _exit;
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}
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}
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ecc_hdbuf[index] = FMC_Bank3_R->HECCR; /* read hardware ecc */
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FMC_Bank3_R->PCR &= ~(1<<6); /* disable ecc */
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}
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i = device->page_size + 0x10;
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rt_hw_nand_delay(10);
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NAND_CMD_AREA = 0x05;
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NAND_DATA_AREA = (rt_uint8_t)i;
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NAND_DATA_AREA = (rt_uint8_t)(i>>8);
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NAND_CMD_AREA = 0xE0;
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rt_hw_nand_delay(10);
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data =(rt_uint8_t*)&ecc_rdbuf[0];
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for (i = 0; i < 4*eccnum; i++)
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{
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*data++ = NAND_ADDR_AREA;
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}
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/* check ecc */
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for(i = 0; i< eccnum; i++)
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{
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if(ecc_rdbuf[i] != ecc_hdbuf[i])
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{
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result = rt_hw_nand_ecc_check(ecc_hdbuf[i], ecc_rdbuf[i], p + NAND_ECC_SECTOR_SIZE*i);
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if (result != RT_EOK)
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{
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goto _exit;
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}
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}
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}
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}
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}
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if (spare && spare_len)
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{
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NAND_CMD_AREA = NAND_AREA_A;
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NAND_DATA_AREA = (rt_uint8_t)0;
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NAND_DATA_AREA = (rt_uint8_t)(0 >> 8);
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NAND_DATA_AREA = (rt_uint8_t)page;
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NAND_DATA_AREA = (rt_uint8_t)(page >> 8);
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NAND_DATA_AREA = (rt_uint8_t)(page >> 16);
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NAND_CMD_AREA = NAND_AREA_TRUE1;
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rt_thread_delay(10);
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for (i = 0; i < spare_len; i ++)
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{
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*spare++ = NAND_ADDR_AREA;
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}
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}
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if (rt_hw_nand_wait_ready() != RT_EOK)
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{
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result = RT_ETIMEOUT;
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goto _exit;
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}
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_exit:
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rt_mutex_release(&_device.lock);
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|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t _write_page(struct rt_mtd_nand_device *device,
|
||
|
|
rt_off_t page,
|
||
|
|
const rt_uint8_t *data,
|
||
|
|
rt_uint32_t data_len,
|
||
|
|
const rt_uint8_t *spare,
|
||
|
|
rt_uint32_t spare_len)
|
||
|
|
{
|
||
|
|
RT_ASSERT(device != RT_NULL);
|
||
|
|
|
||
|
|
rt_err_t result = RT_EOK;
|
||
|
|
rt_uint32_t eccnum;
|
||
|
|
rt_uint32_t i, index;
|
||
|
|
rt_uint32_t tickstart = 0;
|
||
|
|
|
||
|
|
page = page + device->block_start * device->pages_per_block;
|
||
|
|
if (page / device->pages_per_block > device->block_end)
|
||
|
|
{
|
||
|
|
return -RT_EIO;
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_mutex_take(&_device.lock, RT_WAITING_FOREVER);
|
||
|
|
|
||
|
|
if (data && data_len)
|
||
|
|
{
|
||
|
|
NAND_CMD_AREA = NAND_WRITE0;
|
||
|
|
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)0;
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)(0 >> 8);
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)(page & 0xFF);
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)(page >> 8);
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)(page >> 16);
|
||
|
|
|
||
|
|
rt_hw_nand_delay(10);
|
||
|
|
|
||
|
|
if (data_len % NAND_ECC_SECTOR_SIZE)
|
||
|
|
{
|
||
|
|
/* read nand flash */
|
||
|
|
for (i = 0; i < data_len; i++)
|
||
|
|
{
|
||
|
|
NAND_ADDR_AREA = *data++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
eccnum = data_len/NAND_ECC_SECTOR_SIZE;
|
||
|
|
for (index = 0; index < eccnum; index++)
|
||
|
|
{
|
||
|
|
FMC_Bank3_R->PCR |= 1<<6; /* enable ecc */
|
||
|
|
|
||
|
|
for (i = 0; i < NAND_ECC_SECTOR_SIZE; i++)
|
||
|
|
{
|
||
|
|
NAND_ADDR_AREA = *data++;
|
||
|
|
}
|
||
|
|
/* Get tick */
|
||
|
|
tickstart = rt_tick_get();
|
||
|
|
/* Wait until FIFO is empty */
|
||
|
|
while ((FMC_Bank3_R->SR & (1 << 6)) == RESET)
|
||
|
|
{
|
||
|
|
/* Check for the Timeout */
|
||
|
|
if ((rt_tick_get() - tickstart) > 10000)
|
||
|
|
{
|
||
|
|
result = RT_ETIMEOUT;
|
||
|
|
goto _exit;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
ecc_hdbuf[index] = FMC_Bank3_R->HECCR; /* read hardware ecc */
|
||
|
|
FMC_Bank3_R->PCR &= ~(1<<6); /* disable ecc */
|
||
|
|
}
|
||
|
|
|
||
|
|
i = device->page_size + 0x10;
|
||
|
|
rt_hw_nand_delay(10);
|
||
|
|
NAND_CMD_AREA = 0x85;
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)i;
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)(i>>8);
|
||
|
|
rt_hw_nand_delay(10);
|
||
|
|
|
||
|
|
data = (uint8_t*)&ecc_hdbuf[0];
|
||
|
|
|
||
|
|
for (index = 0; index < eccnum; index++)
|
||
|
|
{
|
||
|
|
for (i = 0; i < 4; i++)
|
||
|
|
{
|
||
|
|
NAND_ADDR_AREA = *data++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
NAND_CMD_AREA = NAND_WRITE_TURE1;
|
||
|
|
if (rt_hw_nand_wait_ready() != RT_EOK)
|
||
|
|
{
|
||
|
|
result = -RT_EIO;
|
||
|
|
goto _exit;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (spare && spare_len)
|
||
|
|
{
|
||
|
|
NAND_CMD_AREA = NAND_WRITE0;
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)(4096 & 0xFF);
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)(4096 >> 8);
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)(page & 0xFF);
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)(page >> 8);
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)(page >> 16);
|
||
|
|
|
||
|
|
for (i = 4; i < spare_len; i++)
|
||
|
|
{
|
||
|
|
NAND_ADDR_AREA = spare[i];
|
||
|
|
}
|
||
|
|
NAND_CMD_AREA = NAND_WRITE_TURE1;
|
||
|
|
if (rt_hw_nand_wait_ready() != RT_EOK)
|
||
|
|
{
|
||
|
|
result = -RT_EIO;
|
||
|
|
goto _exit;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
_exit:
|
||
|
|
rt_mutex_release(&_device.lock);
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* erase one block */
|
||
|
|
static rt_err_t _erase_block(struct rt_mtd_nand_device *device, rt_uint32_t block)
|
||
|
|
{
|
||
|
|
RT_ASSERT(device != RT_NULL);
|
||
|
|
unsigned int block_num;
|
||
|
|
rt_err_t result = RT_EOK;
|
||
|
|
|
||
|
|
block = block + device->block_start;
|
||
|
|
block_num = block << 6;
|
||
|
|
|
||
|
|
rt_mutex_take(&_device.lock, RT_WAITING_FOREVER);
|
||
|
|
|
||
|
|
NAND_CMD_AREA = NAND_ERASE0;
|
||
|
|
NAND_DATA_AREA = (uint8_t)block_num;
|
||
|
|
NAND_DATA_AREA = (uint8_t)(block_num >> 8);
|
||
|
|
NAND_DATA_AREA = (uint8_t)(block_num >> 16);
|
||
|
|
NAND_CMD_AREA = NAND_ERASE1;
|
||
|
|
|
||
|
|
rt_thread_delay(NAND_TBERS_DELAY);
|
||
|
|
|
||
|
|
if (rt_hw_nand_wait_ready() != RT_EOK)
|
||
|
|
{
|
||
|
|
result = -RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_mutex_release(&_device.lock);
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t _page_copy(struct rt_mtd_nand_device *device,
|
||
|
|
rt_off_t src_page,
|
||
|
|
rt_off_t dst_page)
|
||
|
|
{
|
||
|
|
RT_ASSERT(device != RT_NULL);
|
||
|
|
rt_err_t result = RT_EOK;
|
||
|
|
rt_uint32_t source_block = 0, dest_block = 0;
|
||
|
|
|
||
|
|
src_page = src_page + device->block_start * device->pages_per_block;
|
||
|
|
dst_page = dst_page + device->block_start * device->pages_per_block;
|
||
|
|
source_block = src_page / device->pages_per_block;
|
||
|
|
dest_block = dst_page / device->pages_per_block;
|
||
|
|
if ((source_block % 2) != (dest_block % 2))
|
||
|
|
{
|
||
|
|
return RT_MTD_ESRC;
|
||
|
|
}
|
||
|
|
|
||
|
|
NAND_CMD_AREA = NAND_MOVEDATA_CMD0;
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)(0 & 0xFF);
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)(0 >> 8);
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)(src_page & 0xFF);
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)(src_page >> 8);
|
||
|
|
NAND_DATA_AREA = (rt_uint8_t)(src_page >> 16);
|
||
|
|
NAND_CMD_AREA = NAND_MOVEDATA_CMD1;
|
||
|
|
|
||
|
|
rt_hw_nand_delay(10);
|
||
|
|
|
||
|
|
NAND_CMD_AREA = NAND_MOVEDATA_CMD2;
|
||
|
|
NAND_DATA_AREA = ((rt_uint8_t)(0 & 0xFF));
|
||
|
|
NAND_DATA_AREA = ((rt_uint8_t)(0 >> 8));
|
||
|
|
NAND_DATA_AREA = ((rt_uint8_t)(dst_page & 0xFF));
|
||
|
|
NAND_DATA_AREA = ((rt_uint8_t)(dst_page >> 8));
|
||
|
|
NAND_DATA_AREA = ((rt_uint8_t)(dst_page >> 16));
|
||
|
|
NAND_CMD_AREA = (NAND_MOVEDATA_CMD3);
|
||
|
|
|
||
|
|
if (rt_hw_nand_wait_ready() != RT_EOK)
|
||
|
|
{
|
||
|
|
result = -RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t _check_block(struct rt_mtd_nand_device *device, rt_uint32_t block)
|
||
|
|
{
|
||
|
|
RT_ASSERT(device != RT_NULL);
|
||
|
|
return (RT_MTD_EOK);
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t _mark_bad(struct rt_mtd_nand_device *device, rt_uint32_t block)
|
||
|
|
{
|
||
|
|
RT_ASSERT(device != RT_NULL);
|
||
|
|
return (RT_MTD_EOK);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct rt_mtd_nand_driver_ops ops =
|
||
|
|
{
|
||
|
|
_read_id,
|
||
|
|
_read_page,
|
||
|
|
_write_page,
|
||
|
|
_page_copy,
|
||
|
|
_erase_block,
|
||
|
|
_check_block,
|
||
|
|
_mark_bad,
|
||
|
|
};
|
||
|
|
static struct rt_mtd_nand_device nand_dev;
|
||
|
|
|
||
|
|
static rt_err_t nand_init(struct rt_mtd_nand_device *device)
|
||
|
|
{
|
||
|
|
RT_ASSERT(device != RT_NULL);
|
||
|
|
uint32_t tempreg = 0;
|
||
|
|
|
||
|
|
rt_hw_nand_gpio_init();
|
||
|
|
|
||
|
|
tempreg |= 0 << 1; /* disable Wait feature enable bit */
|
||
|
|
tempreg |= 0 << 4; /* Data bus width 8*/
|
||
|
|
tempreg |= 0 << 6; /* disable ECC */
|
||
|
|
tempreg |= 1 << 17; /* ECC page 512 BYTE */
|
||
|
|
tempreg |= 5 << 9; /* set TCLR */
|
||
|
|
tempreg |= 5 << 13; /* set TAR */
|
||
|
|
FMC_Bank3_R->PCR = tempreg; /* set nand control register */
|
||
|
|
|
||
|
|
tempreg &= 0;
|
||
|
|
tempreg |= 3 << 0; /* set MEMSET */
|
||
|
|
tempreg |= 5 << 8; /* set MEMWAIT */
|
||
|
|
tempreg |= 2 << 16; /* set MEMHOLD */
|
||
|
|
tempreg |= 3 << 24; /* set MEMHIZ */
|
||
|
|
FMC_Bank3_R->PMEM = tempreg;
|
||
|
|
FMC_Bank3_R->PATT = 0; /* Attribute memory space timing registers */
|
||
|
|
FMC_Bank3_R->PCR |= 1 << 2; /* NAND Flash memory bank enable bit */
|
||
|
|
FMC_Bank1_R->BTCR[0] |= (uint32_t)1 << 31; /* enable fmc */
|
||
|
|
|
||
|
|
rt_hw_nand_reset(); /* reset nand flash*/
|
||
|
|
rt_thread_delay(100);
|
||
|
|
|
||
|
|
/* read id */
|
||
|
|
_read_id(&nand_dev);
|
||
|
|
|
||
|
|
if (_device.id != MT29F8G08ABACAH4)
|
||
|
|
{
|
||
|
|
LOG_E("nand id 0x%08x not support", _device.id);
|
||
|
|
return RT_ERROR; /* can't find nand flash */
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_hw_nand_set_mode(4); /* set mode 4, high speed mode*/
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
int rt_hw_nand_init(void)
|
||
|
|
{
|
||
|
|
rt_err_t result = RT_EOK;
|
||
|
|
|
||
|
|
rt_pin_mode(NAND_RB_PIN, PIN_MODE_INPUT_PULLUP); /* nand flash R/B pin */
|
||
|
|
|
||
|
|
result = nand_init(&nand_dev);
|
||
|
|
if (result != RT_EOK)
|
||
|
|
{
|
||
|
|
LOG_D("nand flash init error!");
|
||
|
|
return RT_ERROR;
|
||
|
|
}
|
||
|
|
rt_mutex_init(&_device.lock, "nand", RT_IPC_FLAG_FIFO);
|
||
|
|
|
||
|
|
nand_dev.page_size = 4096;
|
||
|
|
nand_dev.pages_per_block = 224;
|
||
|
|
nand_dev.plane_num = 2;
|
||
|
|
nand_dev.oob_size = 64;
|
||
|
|
nand_dev.oob_free = 64 - ((4096) * 3 / 256);
|
||
|
|
nand_dev.block_start = 0;
|
||
|
|
nand_dev.block_end = 4095;
|
||
|
|
|
||
|
|
nand_dev.block_total = nand_dev.block_end - nand_dev.block_start;
|
||
|
|
nand_dev.ops = &ops;
|
||
|
|
|
||
|
|
result = rt_mtd_nand_register_device("nand", &nand_dev);
|
||
|
|
if (result != RT_EOK)
|
||
|
|
{
|
||
|
|
rt_device_unregister(&nand_dev.parent);
|
||
|
|
return RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_kprintf("nand flash init success, id: 0x%08x\n", _device.id);
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
INIT_DEVICE_EXPORT(rt_hw_nand_init);
|
||
|
|
|
||
|
|
#endif
|