550 lines
15 KiB
ArmAsm
550 lines
15 KiB
ArmAsm
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/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Origin Authors: Loongson Technology Corporation Limited,
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* caogos <1207280597@qq.com>, Jiaxun Yang <jiaxun.yang@flygoat.com>,
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*
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* Also thanks to Liu Shiwei <liushiwei@gmail.com> and other Loongson
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* Community developers.
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*
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* Change Logs:
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* Date Author Notes
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* 2019-12-04 Jiaxun Yang Initial version
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*/
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#include <rtconfig.h>
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#ifdef RT_USING_SELF_BOOT
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#ifndef __ASSEMBLY__
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#define __ASSEMBLY__
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#endif
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#include <mips.h>
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#include "selfboot.h"
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#include "ls1c.h"
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#include "cache.h"
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/*
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* Register usage:
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*
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* s0 link versus load offset, used to relocate absolute adresses.
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* s1 free
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* s2 memory size
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* s3 free
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* s4 free
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* s5 dbg
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* s6 sdCfg
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* s7 rasave
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* s8 free
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*/
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#define tmpsize s1
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#define msize s2
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#define bonito s4
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#define dbg s5
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#define sdCfg s6
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/* Macros */
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#ifdef RT_SELF_BOOT_DEBUG
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#define PRINTSTR(str) \
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.pushsection .selfboot_data; .align 4; 98: .asciz str; .popsection; la a0, 98b; bal stringserial; nop
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#else
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#define PRINTSTR(x)
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#endif
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#define DELAY(count) \
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li v0, count; \
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99: \
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bnez v0, 99b;\
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addiu v0, -1
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.section ".selfboot", "ax"
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.set noreorder
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.set mips32
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.globl _start
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.extern start
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_start:
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/* NMI/Reset vector starts here*/
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mtc0 zero, CP0_STATUS /* set cp0 status register to zero */
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mtc0 zero, CP0_CAUSE /* set cp0 cause register to zero */
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li t0, ST0_BEV /* set exception vector to in flash location */
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mtc0 t0, CP0_STATUS
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/* Speed up SPI reading */
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li t0, 0xbfe80000 /* load SPI0 controler base address to t0 */
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li t1, 0x17 /* load "div 4, fast_read + burst_en + memory_en double I/O" to
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* to t0 for write, not all the flash chips support this mode */
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sb t1, 0x4(t0) /* set sfc_param register */
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li t1, 0x05
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sb t1, 0x6(t0) /* set sfc_timing register */
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bal locate /* branch out of vector and get current address to ra */
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nop
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/* in-flash exception vectors start here */
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/* save the exception types to a0 and print out PANIC message in exc_common */
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#define EXC_TLB_REFILL 0x0
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#define EXC_CACHE_ERR 0x1
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#define EXC_GEN 0x2
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#define EXC_INT 0x3
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.org 0x200 /* 0xbfc00200 TLB_REFILL exception */
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li a0, EXC_TLB_REFILL
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b exc_common
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nop
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.org 0x300 /* 0xbfc00300 Cache Error exception */
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li a0, EXC_CACHE_ERR
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b exc_common
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nop
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.org 0x380 /* 0xbfc00300 General exception */
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li a0,EXC_GEN
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b exc_common
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nop
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.org 0x400 /* 0xbfc00400 Interrupt exception */
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li a0, EXC_INT
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b exc_common
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nop
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1: /* impossible to reach here, so make a dead loop */
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b 1b
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nop
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exc_common: /* try one cause and pass to next */
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li s1, EXC_TLB_REFILL
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bne a0, s1, 1f
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nop
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PRINTSTR("\r\nEARLY_PANIC: Exception TLB Refill")
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b print_cause
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nop
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1:
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li s1, EXC_CACHE_ERR
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bne a0, s1, 1f
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nop
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PRINTSTR("\r\nEARLY_PANIC: CACHE Error: ")
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mfc0 a0, CP0_CACHEERR
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bal hexserial
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nop
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b print_cause
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nop
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1:
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li s1, EXC_GEN
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bne a0, s1, 1f
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nop
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PRINTSTR("\r\nEARLY_PANIC: General Exception")
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b print_cause
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nop
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1:
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li s1, EXC_INT
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bne a0, s1, print_cause /* if all exceptions in a0 not reached,
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* print_cause directly*/
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nop
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PRINTSTR("\r\nEARLY_PANIC: Interrupt Exception")
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print_cause:
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PRINTSTR("\r\nCAUSE=")
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mfc0 a0, CP0_CAUSE
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bal hexserial
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nop
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PRINTSTR("\r\nSTATUS=")
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mfc0 a0, CP0_STATUS
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bal hexserial
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nop
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PRINTSTR("\r\nERRORPC=")
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mfc0 a0, CP0_ERROREPC
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bal hexserial
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nop
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PRINTSTR("\r\nEPC=")
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mfc0 a0, CP0_EPC
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bal hexserial
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nop
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PRINTSTR("\r\nBADADDR=")
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mfc0 a0, CP0_BADVADDR
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bal hexserial
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nop
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PRINTSTR("\r\nEARLY: LOOP! Noting to do")
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1: /* Make a dead loop here, wait user to reset the MCU */
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b 1b
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nop
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/* locate here, continue the start progress */
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locate:
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/* fix the absolute address by ra */
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la s0, start /* s0 = start */
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subu s0, ra, s0 /* s0 = ra - s0 */
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and s0, 0xffff0000 /* s0 = s0 & 0xffff0000 */
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li t0, 0xbfe78030 /* load PLL/SDRAM freq config register base to t0 */
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li t2, (0x80000008 | (PLL_MULT << 8) | (0x3 << 2) | SDRAM_DIV) /* Set PLL
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* MULT and PLL DIV */
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li t3, (0x00008003 | (CPU_DIV << 8)) /* set CPU DEV */
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li t1, 0x2
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sw t1, 0x4(t0) /* disable CPU_DIV_VALID firstly for adjustment */
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sw t2, 0x0(t0) /* write START_FREQ */
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sw t3, 0x4(t0) /* write CLK_DIV_PARAM */
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/* start to initialize debug uart port */
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la v0, LS1C_UART2_BASE /* load UART2 base to v0, only UART2 can be debug port */
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1:
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li v1, FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4 /* clear Rx,Tx FIFO
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* declear 4 bit int trigger */
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sb v1, LS1C_UART_FCR_OFFSET(v0) /* write FCR (FIFO control register) */
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li v1, CFCR_DLAB /* reach freq div register */
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sb v1, LS1C_UART_LCR_OFFSET(v0) /* write LCR (Line control register)*/
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/* Set UART2 reuse with GPIO36,37*/
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li a0, LS1C_CBUS_FIRST1 /* load CBUS_FIRST1 offset to a0 */
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lw a1, 0x10(a0) /* load value from CBUS_SECOND1 to a1 */
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ori a1, 0x30 /* a1 |= 0x30, GPIO36,37 as secondary function */
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sw a1, 0x10(a0) /* write back modified CBUS_SECOND1 from a1 */
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/* Caculate PLL and bit rate */
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li a0, 0xbfe78030 /* load START_FREQ register address to a0 */
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lw a1, 0(a0) /* load value from START_FREQ to a1*/
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srl a1, 8 /* a1 >>= 8 */
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andi a1, 0xff /* a1 &= 0xff, as a1=PLL_MULT */
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li a2, APB_CLK /* a2 = APB_CLK = 24Mhz (External Clock Freq) */
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srl a2, 2 /* a2 = a2 >> 2 = APB_CLK/4 */
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multu a1, a2 /* hilo = a1 * a2 = PLL_MULT * APB_CLK /4 */
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mflo v1 /* v1 = lo. put low 32 bit of a1 * a2 to v1 as PLL freq */
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/* Determine if we need to devide the clock */
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lw a1, 4(a0) /* load value frm CLK_DIV_PARAM to a1 */
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andi a2, a1, DIV_CPU_SEL /* a2 = a1 & DIV_CPU_SEL, if CPU_SEL=1, devide the clock,
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* if CPU_SEL=0, bypass the clock */
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bnez a2, 1f /* if (a2 != 0), branch to next tag 1 */
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nop
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li v1, APB_CLK /* v1 = APB_CLK */
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b 3f
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nop
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1: /* Determine if the CPU_DIV is valid*/
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andi a2, a1, DIV_CPU_EN /* a2 = a1 & DIV_CPU_EN */
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bnez a2, 2f /* if (a2 != 0), branch to next tag 2 */
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nop
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srl v1, 1 /* v1 >>= 1, so v1 = APB_CLK/4 * PLL_MULT/2 */
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b 3f
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nop
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2: /* caculate CPU freq */
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andi a1, DIV_CPU /* a1 &= DIV_CPU */
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srl a1, DIV_CPU_SHIFT /* a1 >>= DIV_CPU_SHIFT */
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divu v1, a1 /* lo = v1/a1, hi = v1 % a1 */
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mflo v1 /* v1 = lo, CPU Freq */
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3:
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li a1, (16 * EARLY_DEBUG_BAUD) /* a1 = 16 * BIT RATE */
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divu v1, v1, a1 /* v1 = v1 / a1 */
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srl v1, 1 /* v1 >>= 1 */
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sb v1, LS1C_UART_LSB_OFFSET(v0) /* write 8bit low into LSB */
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srl v1, 8 /* v1 >>= 8 */
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sb v1, LS1C_UART_MSB_OFFSET(v0) /* write 8bit low into MSB */
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li v1, CFCR_8BITS /* 8n1, no check */
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sb v1, LS1C_UART_LCR_OFFSET(v0) /* write to LCR (Line Control Register) */
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#ifdef EARLY_DEBUG_UART_FLOW_CTRL
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li v1, MCR_DTR|MCR_RTS /* valid DTR and RTS */
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sb v1, LS1C_UART_MCR_OFFSET(v0) /* write to MCR (MODEM Control Register) */
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#endif
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li v1, 0x0 /* disable all the interruptions */
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sb v1, LS1C_UART_IER_OFFSET(v0) /* write to IER (Interruptions Enable Registers) */
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PRINTSTR("\r\INFO: Loongson 1C300 Starting :) \r\n")
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/* disable all GPIOs for conflict functions */
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li a0,0xbfd00000
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sw zero,0x10c0(a0) /* disable GPIO 0-31 */
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sw zero,0x10c4(a0) /* disable GPIO 32-63 */
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sw zero,0x10c8(a0) /* disable GPIO 64-95 */
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sw zero,0x10cc(a0)
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li t0, 0xffffffff
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sw t0, 0x10d0(a0)
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sw t0, 0x10d4(a0)
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sw t0, 0x10d8(a0)
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sw t0, 0x10dc(a0)
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sw t0, 0x10f0(a0)
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sw t0, 0x10f4(a0)
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sw t0, 0x10f8(a0)
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sw t0, 0x10fc(a0)
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PRINTSTR("\r\INFO: All GPIOs are disabled\r\n")
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/* SDRAM initialize starts here */
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li msize, MEM_SIZE
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#ifdef EJTAG_SEL_AS_SDRAM_CS1
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li a0, 0xbfd011c0
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lw a1, 0x40(a0)
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ori a1, 0x01
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sw a1, 0x40(a0)
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PRINTSTR("\r\INFO: EJTAG_SEL PIN as SDRAM_CS1\r\n")
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#endif
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/*
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* recommanded by user manual, we should write SD_CONFIG[31:0] first, then
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* write SD_CONFIG[63:32]. Repeat writing for three times, valid the config in
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* the last time.
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*/
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/* write first time */
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li t1, 0xbfd00410 /* load SD_CONFIG[31:0] address to t1 */
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li a1, SD_PARA0 /* get the memory config from macro SD_PARA0 */
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sw a1, 0x0(t1) /* write to SD_CONFIG[31:0] */
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li a1, SD_PARA1
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sw a1, 0x4(t1) /* write to SD_CONFIG[63:32] with offset */
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PRINTSTR("\r\INFO: SDRAM Config Pass1\r\n")
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/* write second time,the same */
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li a1, SD_PARA0
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sw a1, 0x0(t1)
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li a1, SD_PARA1
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sw a1, 0x4(t1)
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PRINTSTR("\r\INFO: SDRAM Config Pass2\r\n")
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/* write third time, enable controller this time */
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li a1, SD_PARA0
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sw a1, 0x0(t1)
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li a1, SD_PARA1_EN /* enable it */
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sw a1, 0x4(t1)
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PRINTSTR("\r\INFO: SDRAM initialize compeleted\r\n")
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/* initialize cache */
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bal cache_init /* branch to cache_init */
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nop
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/* enable cache */
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mfc0 a0, CP0_CONFIG /* load cp0 config to a0 */
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and a0, a0, ~((1<<12) | 7) /* a0 = a0 & ~((1<<12) | 7) */
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or a0, a0, 2 /* a0 |= 2 */
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mtc0 a0, CP0_CONFIG /* write back to CP0 config */
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/*
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* relocate: copy selfboot code to memory in kseg0, fix PC and jump to kseg0.
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* in order to speed up the copy progress, we will execute copy code in kseg0
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*/
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PRINTSTR("\r\INFO: Relocating")
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la t0, text_copy_start /* load the adress of start tag to t0 */
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move t2, t0
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addu t0, s0 /* correct t0 address in rom by s0 */
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la t1, text_copy_end
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selfboot_copy_loop:
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lw v0, (t0) /* copy from memory address in t0 to register v0 */
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|
|
sw v0, (t2) /* write data in register v0 to memory address t0 */
|
||
|
|
addiu t0, 0x4 /* t0 moves forward 4 bytes */
|
||
|
|
addiu t2, 0x4 /* t2 moves forward 4 bytes */
|
||
|
|
ble t2, t1, selfboot_copy_loop /* if t1 <= t2 loop to continue the copy */
|
||
|
|
nop
|
||
|
|
|
||
|
|
la t0, text_copy_start /* load start address to t0 */
|
||
|
|
jr t0 /* jump to 122 in kseg0 to start copy code progress */
|
||
|
|
nop
|
||
|
|
|
||
|
|
text_copy_start:
|
||
|
|
/* Copy code to memory*/
|
||
|
|
la a0, start /* load address of start symbol to a0 */
|
||
|
|
addu a1, a0, s0 /* correct a0 to address in flash */
|
||
|
|
la a2, _edata /* load symbol _edata address to a2 */
|
||
|
|
subu t1, a2, a0 /* t1 = a2 - a0, the space of text area */
|
||
|
|
|
||
|
|
move t0, a0 /* the start address in ram */
|
||
|
|
move t1, a1 /* the start address in rom */
|
||
|
|
move t2, a2 /* the end address in rom (symbol _edata) */
|
||
|
|
|
||
|
|
/* copy text section */
|
||
|
|
1:
|
||
|
|
and t3, t0, 0x0000ffff /* t3 = t0 & 0x0000ffff, get low 16 bit */
|
||
|
|
bnez t3, 2f /* if t3 != 0, jump to next tag 2 */
|
||
|
|
nop
|
||
|
|
2:
|
||
|
|
lw t3, 0(t1) /* copy 4 bit from memory address t1 to register t3 */
|
||
|
|
nop
|
||
|
|
sw t3, 0(t0) /* copy 4 bit from register t3 to memory address in t0 */
|
||
|
|
addu t0, 4 /* t0 move forward 4 bytes */
|
||
|
|
addu t1, 4 /* t1 move forward 4 bytes */
|
||
|
|
bne t2, t0, 1b /* if t2 != t0, branch to last tag 1 to continue copy */
|
||
|
|
nop
|
||
|
|
/* copy text section done. */
|
||
|
|
|
||
|
|
move a0, msize /* a0 = msize, will be passed to main */
|
||
|
|
srl a0, 20 /* a0 >>= 20, convert to unit in MB */
|
||
|
|
|
||
|
|
/* execute main */
|
||
|
|
la v0, _rtthread_entry /* load address of function main to v0 */
|
||
|
|
jalr v0 /* call address in v0, congrats! all low_level things done!
|
||
|
|
* switch brain out of assembly */
|
||
|
|
nop
|
||
|
|
text_copy_end: /* end of self-copy in memory */
|
||
|
|
|
||
|
|
loop: /* impossible to reach here, make a dead loop */
|
||
|
|
b loop
|
||
|
|
nop
|
||
|
|
|
||
|
|
/* functions here */
|
||
|
|
|
||
|
|
LEAF(stringserial) /* print out the string in address passed in a0 */
|
||
|
|
nop
|
||
|
|
move a2, ra /* save the return address to a2 */
|
||
|
|
addu a1, a0, s0 /* correct the address in ROM */
|
||
|
|
lbu a0, 0(a1) /* read the first byte in memory address a1 to a0 */
|
||
|
|
1:
|
||
|
|
beqz a0, 2f /* if a0 == 0, jump to next tag 2, empty char */
|
||
|
|
nop
|
||
|
|
bal tgt_putchar /* print a char */
|
||
|
|
addiu a1, 1 /* a1 += 1 move forward to next byte */
|
||
|
|
b 1b /* branch to the last tag 1, continue */
|
||
|
|
lbu a0, 0(a1) /* load the next bit from address a1 to a0, in delay solt,
|
||
|
|
* will be execuated before branch */
|
||
|
|
2:
|
||
|
|
j a2 /* return */
|
||
|
|
nop
|
||
|
|
END(stringserial)
|
||
|
|
|
||
|
|
|
||
|
|
LEAF(hexserial) /* print out single hex char passed in register a0 */
|
||
|
|
nop
|
||
|
|
move a2, ra /* move return address from ra to a2 */
|
||
|
|
move a1, a0 /* move hex char from register a0 to a1 */
|
||
|
|
li a3, 7 /* load 7 to a3 */
|
||
|
|
1:
|
||
|
|
rol a0, a1, 4 /* rotate left ward shift for 4 bit in a1 to a0 */
|
||
|
|
move a1, a0
|
||
|
|
and a0, 0xf
|
||
|
|
la v0, hexchar
|
||
|
|
|
||
|
|
.pushsection .selfboot_data
|
||
|
|
.align 4
|
||
|
|
hexchar:
|
||
|
|
.ascii "0123456789abcdef"
|
||
|
|
.popsection
|
||
|
|
.align 4
|
||
|
|
|
||
|
|
addu v0, s0
|
||
|
|
addu v0, a0
|
||
|
|
bal tgt_putchar
|
||
|
|
lbu a0, 0(v0)
|
||
|
|
|
||
|
|
bnez a3, 1b
|
||
|
|
addu a3, -1
|
||
|
|
|
||
|
|
j a2
|
||
|
|
nop
|
||
|
|
END(hexserial)
|
||
|
|
|
||
|
|
LEAF(tgt_putchar) /* print out a char in a0 */
|
||
|
|
la v0, LS1C_UART2_BASE /* load UART register address to a0 */
|
||
|
|
lbu v1, LS1C_UART_LSR_OFFSET(v0) /* load value from LSR to v0 */
|
||
|
|
1:
|
||
|
|
and v1, LSR_TXRDY /* v1 &= LSR_TXRDY determine wether we can send by TFE bit */
|
||
|
|
beqz v1, 1b /* if (v1 == 0) jump to last 1 tag, waiting until TFE is 1 */
|
||
|
|
lbu v1, LS1C_UART_LSR_OFFSET(v0) /* load value from LSR to v0 again, in delay solt */
|
||
|
|
|
||
|
|
sb a0, LS1C_UART_DAT_OFFSET(v0) /* write a0 into DAT, send out */
|
||
|
|
j ra /* */
|
||
|
|
nop
|
||
|
|
END(tgt_putchar)
|
||
|
|
|
||
|
|
LEAF(CPU_SetSR) /* modify SR value, arg 1 = set bits, arg 2 = clear bits. */
|
||
|
|
mfc0 v0, CP0_STATUS
|
||
|
|
not v1, a1
|
||
|
|
and v1, v0
|
||
|
|
or v1, a0
|
||
|
|
mtc0 v1, CP0_STATUS
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
j ra
|
||
|
|
nop
|
||
|
|
END(CPU_SetSR)
|
||
|
|
|
||
|
|
cache_init:
|
||
|
|
move t1, ra
|
||
|
|
####part 2####
|
||
|
|
cache_detect_4way:
|
||
|
|
mfc0 t4, CP0_CONFIG,1 /* move CP0 CONFIG to t4 */
|
||
|
|
lui v0, 0x7 /* v0 = 0x7 << 16 */
|
||
|
|
and v0, t4, v0 /* v0 = t4 & v0 */
|
||
|
|
srl t3, v0, 16 /* t3 = v0 >> 16 Icache组相联数 IA */
|
||
|
|
|
||
|
|
li t5, 0x800 //32*64
|
||
|
|
srl v1, t4,22 //v1 = t4 >> 22
|
||
|
|
andi v1, 7 //Icache每路的组数 64x2^S IS
|
||
|
|
sll t5, v1 //InstCacheSetSize
|
||
|
|
sll t5, t3 //t5 InstCacheSize
|
||
|
|
|
||
|
|
|
||
|
|
andi v0, t4, 0x0380
|
||
|
|
srl t7, v0, 7 //DA
|
||
|
|
|
||
|
|
li t6, 0x800 // 32*64
|
||
|
|
srl v1, t4,13
|
||
|
|
andi v1, 7 //DS
|
||
|
|
sll t6, v1 // DataCacheSetSize
|
||
|
|
sll t6, t7 // t5 DataCacheSize
|
||
|
|
|
||
|
|
####part 3####
|
||
|
|
lui a0, 0x8000 //a0 = 0x8000 << 16
|
||
|
|
addu a1, $0, t5
|
||
|
|
addu a2, $0, t6
|
||
|
|
cache_init_d2way:
|
||
|
|
/* a0=0x80000000, a1=icache_size, a2=dcache_size */
|
||
|
|
/* a3, v0 and v1 used as local registers */
|
||
|
|
mtc0 $0, CP0_TAGHI
|
||
|
|
addu v0, $0, a0 /* v0 = 0 + a0 */
|
||
|
|
addu v1, a0, a2 /* v1 = a0 + a2 */
|
||
|
|
1: slt a3, v0, v1 /* a3 = v0 < v1 ? 1 : 0 */
|
||
|
|
beq a3, $0, 1f /* if (a3 == 0) goto 1f */
|
||
|
|
nop
|
||
|
|
mtc0 $0, CP0_TAGLO
|
||
|
|
cache Index_Store_Tag_D, 0x0(v0) /* 1 way */
|
||
|
|
4: beq $0, $0, 1b
|
||
|
|
addiu v0, v0, 0x20
|
||
|
|
1:
|
||
|
|
cache_flush_i2way:
|
||
|
|
addu v0, $0, a0
|
||
|
|
addu v1, a0, a1
|
||
|
|
1:
|
||
|
|
slt a3, v0, v1
|
||
|
|
beq a3, $0, 1f
|
||
|
|
nop
|
||
|
|
cache Index_Invalidate_I, 0x0(v0) /* 1 way */
|
||
|
|
4:
|
||
|
|
beq $0, $0, 1b
|
||
|
|
addiu v0, v0, 0x20
|
||
|
|
1:
|
||
|
|
cache_flush_d2way:
|
||
|
|
addu v0, $0, a0
|
||
|
|
addu v1, a0, a2
|
||
|
|
1: slt a3, v0, v1
|
||
|
|
beq a3, $0, 1f
|
||
|
|
nop
|
||
|
|
cache Index_Writeback_Inv_D, 0x0(v0) /* 1 way */
|
||
|
|
4: beq $0, $0, 1b
|
||
|
|
addiu v0, v0, 0x20
|
||
|
|
|
||
|
|
1:
|
||
|
|
cache_init_finish:
|
||
|
|
jr t1
|
||
|
|
nop
|
||
|
|
#endif
|