388 lines
11 KiB
C
388 lines
11 KiB
C
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/*!
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\file gd32f3x0_dac.c
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\brief DAC driver
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\version 2017-06-06, V1.0.0, firmware for GD32F3x0
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\version 2019-06-01, V2.0.0, firmware for GD32F3x0
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifdef GD32F350
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#include "gd32f3x0_dac.h"
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/*!
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\brief deinitialize DAC
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_deinit(void)
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{
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rcu_periph_reset_enable(RCU_DACRST);
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rcu_periph_reset_disable(RCU_DACRST);
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}
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/*!
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\brief enable DAC
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_enable(void)
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{
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DAC_CTL |= DAC_CTL_DEN;
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}
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/*!
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\brief disable DAC
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_disable(void)
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{
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DAC_CTL &= ~DAC_CTL_DEN;
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}
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/*!
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\brief enable DAC DMA
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_dma_enable(void)
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{
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DAC_CTL |= DAC_CTL_DDMAEN;
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}
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/*!
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\brief disable DAC DMA
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_dma_disable(void)
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{
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DAC_CTL &= ~DAC_CTL_DDMAEN;
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}
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/*!
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\brief enable DAC output buffer
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_output_buffer_enable(void)
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{
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DAC_CTL &= ~DAC_CTL_DBOFF;
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}
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/*!
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\brief disable DAC output buffer
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_output_buffer_disable(void)
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{
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DAC_CTL |= DAC_CTL_DBOFF;
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}
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/*!
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\brief enable DAC trigger
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_trigger_enable(void)
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{
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DAC_CTL |= DAC_CTL_DTEN;
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}
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/*!
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\brief disable DAC trigger
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_trigger_disable(void)
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{
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DAC_CTL &= ~DAC_CTL_DTEN;
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}
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/*!
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\brief enable DAC software trigger
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_software_trigger_enable(void)
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{
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DAC_SWT |= DAC_SWT_SWTR;
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}
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/*!
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\brief disable DAC software trigger
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_software_trigger_disable(void)
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{
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DAC_SWT &= ~DAC_SWT_SWTR;
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}
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/*!
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\brief enable DAC interrupt(DAC DMA underrun interrupt)
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_interrupt_enable(void)
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{
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DAC_CTL |= DAC_CTL_DDUDRIE;
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}
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/*!
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\brief disable DAC interrupt(DAC DMA underrun interrupt)
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_interrupt_disable(void)
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{
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DAC_CTL &= ~DAC_CTL_DDUDRIE;
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}
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/*!
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\brief set DAC tgigger source
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\param[in] triggersource: external triggers of DAC
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\arg DAC_TRIGGER_T1_TRGO: trigger source is TIMER1 TRGO
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\arg DAC_TRIGGER_T2_TRGO: trigger source is TIMER2 TRGO
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\arg DAC_TRIGGER_T5_TRGO: trigger source is TIMER5 TRGO
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\arg DAC_TRIGGER_T14_TRGO: trigger source is TIMER14 TRGO
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\arg DAC_TRIGGER_EXTI_9: trigger source is EXTI interrupt line9 event
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\arg DAC_TRIGGER_SOFTWARE: software trigger
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\param[out] none
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\retval none
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*/
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void dac_trigger_source_config(uint32_t triggersource)
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{
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DAC_CTL &= ~DAC_CTL_DTSEL;
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DAC_CTL |= triggersource;
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}
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/*!
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\brief configure DAC wave mode
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\param[in] wave_mode
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\arg DAC_WAVE_DISABLE: wave disable
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\arg DAC_WAVE_MODE_LFSR: LFSR noise mode
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\arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode
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\param[out] none
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\retval none
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*/
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void dac_wave_mode_config(uint32_t wave_mode)
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{
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DAC_CTL &= ~DAC_CTL_DWM;
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DAC_CTL |= wave_mode;
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}
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/*!
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\brief configure DAC wave bit width
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\param[in] bit_width
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\arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1
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\arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2
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\arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3
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\arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4
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\arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5
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\arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6
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\arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7
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\arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8
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\arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9
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\arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10
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\arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11
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\arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12
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\param[out] none
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\retval none
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*/
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void dac_wave_bit_width_config(uint32_t bit_width)
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{
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DAC_CTL &= ~DAC_CTL_DWBW;
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DAC_CTL |= bit_width;
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}
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/*!
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\brief configure DAC LFSR noise mode
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\param[in] unmask_bits
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\arg DAC_LFSR_BIT0: unmask the LFSR bit0
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\arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0]
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\arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0]
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\arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0]
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\arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0]
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\arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0]
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\arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0]
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\arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0]
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\arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0]
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\arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0]
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\arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0]
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\arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0]
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\param[out] none
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\retval none
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*/
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void dac_lfsr_noise_config(uint32_t unmask_bits)
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{
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DAC_CTL &= ~DAC_CTL_DWBW;
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DAC_CTL |= unmask_bits;
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}
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/*!
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\brief configure DAC triangle noise mode
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\param[in] amplitude
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\arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1
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\arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3
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\arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7
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\arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15
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\arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31
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\arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63
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\arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127
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\arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255
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\arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511
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\arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023
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\arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047
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\arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095
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\param[out] none
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\retval none
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*/
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void dac_triangle_noise_config(uint32_t amplitude)
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{
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DAC_CTL &= ~DAC_CTL_DWBW;
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DAC_CTL |= amplitude;
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}
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/*!
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\brief get DAC output value
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\param[in] none
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\param[out] none
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\retval DAC output data
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*/
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uint16_t dac_output_value_get(void)
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{
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uint16_t data = 0U;
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data = (uint16_t)DAC_DO;
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return data;
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}
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/*!
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\brief get the specified DAC flag(DAC DMA underrun flag)
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\param[in] none
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\param[out] none
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\retval the state of dac bit(SET or RESET)
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*/
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FlagStatus dac_flag_get(void)
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{
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/* check the DMA underrun flag */
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if((uint8_t)RESET != (DAC_STAT & DAC_STAT_DDUDR)){
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return SET;
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}else{
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return RESET;
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}
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}
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/*!
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\brief clear the specified DAC flag(DAC DMA underrun flag)
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_flag_clear(void)
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{
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DAC_STAT |= DAC_STAT_DDUDR;
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}
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/*!
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\brief get the specified DAC interrupt flag(DAC DMA underrun interrupt flag)
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\param[in] none
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\param[out] none
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\retval the state of DAC interrupt flag(SET or RESET)
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*/
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FlagStatus dac_interrupt_flag_get(void)
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{
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FlagStatus temp_flag = RESET;
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uint32_t ddudr_flag = 0U, ddudrie_flag = 0U;
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/* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */
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ddudr_flag = DAC_STAT & DAC_STAT_DDUDR;
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ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE;
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if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){
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temp_flag = SET;
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}
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return temp_flag;
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}
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/*!
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\brief clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag)
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_interrupt_flag_clear(void)
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{
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DAC_STAT |= DAC_STAT_DDUDR;
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}
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/*!
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\brief set DAC data holding register value
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\param[in] dac_align
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\arg DAC_ALIGN_8B_R: data right 8b alignment
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\arg DAC_ALIGN_12B_R: data right 12b alignment
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\arg DAC_ALIGN_12B_L: data left 12b alignment
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\param[in] data: data to be loaded
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\param[out] none
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\retval none
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*/
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void dac_data_set(uint32_t dac_align, uint16_t data)
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{
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switch(dac_align){
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/* data right 12b alignment */
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case DAC_ALIGN_12B_R:
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DAC_R12DH = data;
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break;
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/* data left 12b alignment */
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case DAC_ALIGN_12B_L:
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DAC_L12DH = data;
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break;
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|
/* data right 8b alignment */
|
||
|
|
case DAC_ALIGN_8B_R:
|
||
|
|
DAC_R8DH = data;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* GD32F350 */
|