290 lines
19 KiB
C
290 lines
19 KiB
C
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/*!
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\file gd32f10x_dma.h
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\brief definitions for the DMA
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\version 2014-12-26, V1.0.0, firmware for GD32F10x
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\version 2017-06-20, V2.0.0, firmware for GD32F10x
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\version 2018-07-31, V2.1.0, firmware for GD32F10x
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F10X_DMA_H
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#define GD32F10X_DMA_H
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#include "gd32f10x.h"
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/* DMA definitions */
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#define DMA0 (DMA_BASE) /*!< DMA0 base address */
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#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */
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/* registers definitions */
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#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */
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#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */
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#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */
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#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */
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#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */
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#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */
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#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */
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#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */
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#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */
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#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */
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#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */
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#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */
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#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */
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#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */
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#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */
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#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */
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#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */
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#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */
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#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */
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#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */
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#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */
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#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */
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#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */
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#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */
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#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */
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#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */
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#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */
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#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */
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#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */
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#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */
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/* bits definitions */
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/* DMA_INTF */
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#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */
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#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */
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#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */
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#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */
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/* DMA_INTC */
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#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */
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#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */
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#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */
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#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */
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/* DMA_CHxCTL, x=0..6 */
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#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */
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#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */
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#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */
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#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */
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#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */
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#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */
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#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */
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#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */
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#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */
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#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */
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#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */
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#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */
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/* DMA_CHxCNT, x=0..6 */
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#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
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/* DMA_CHxPADDR, x=0..6 */
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#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
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/* DMA_CHxMADDR, x=0..6 */
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#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */
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/* constants definitions */
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/* DMA channel select */
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typedef enum
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{
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DMA_CH0 = 0, /*!< DMA channel 0 */
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DMA_CH1, /*!< DMA channel 1 */
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DMA_CH2, /*!< DMA channel 2 */
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DMA_CH3, /*!< DMA channel 3 */
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DMA_CH4, /*!< DMA channel 4 */
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DMA_CH5, /*!< DMA channel 5 */
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DMA_CH6 /*!< DMA channel 6 */
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} dma_channel_enum;
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/* DMA initialize struct */
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typedef struct
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{
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uint32_t periph_addr; /*!< peripheral base address */
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uint32_t periph_width; /*!< transfer data size of peripheral */
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uint32_t memory_addr; /*!< memory base address */
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uint32_t memory_width; /*!< transfer data size of memory */
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uint32_t number; /*!< channel transfer number */
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uint32_t priority; /*!< channel priority level */
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uint8_t periph_inc; /*!< peripheral increasing mode */
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uint8_t memory_inc; /*!< memory increasing mode */
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uint8_t direction; /*!< channel data transfer direction */
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} dma_parameter_struct;
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#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */
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/* DMA_register address */
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#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */
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#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */
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#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */
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#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */
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/* DMA reset value */
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#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
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#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
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#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
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#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
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#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
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DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */
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/* DMA_INTF register */
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/* interrupt flag bits */
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#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
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#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */
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#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */
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#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */
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/* flag bits */
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#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
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#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */
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#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */
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#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */
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/* DMA_CHxCTL register */
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/* interrupt enable bits */
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#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */
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#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */
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#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */
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/* transfer direction */
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#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */
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#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */
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/* circular mode */
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#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000000U) /*!< circular mode disable */
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#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000001U) /*!< circular mode enable */
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/* peripheral increasing mode */
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#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is fixed address mode */
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#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is increasing address mode */
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/* memory increasing mode */
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#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of memory is fixed address mode */
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#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of memory is increasing address mode */
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/* transfer data size of peripheral */
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#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */
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#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */
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#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */
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#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */
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/* transfer data size of memory */
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#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */
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#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */
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#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */
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#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */
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/* channel priority level */
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#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */
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#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */
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#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */
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#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */
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#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */
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/* memory to memory mode */
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#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) /*!< disable memory to memory mode */
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#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) /*!< enable memory to memory mode */
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/* DMA_CHxCNT register */
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/* transfer counter */
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#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */
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/* function declarations */
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/* DMA deinitialization and initialization functions */
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/* deinitialize DMA a channel registers */
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void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
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/* initialize the parameters of DMA struct with the default values */
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void dma_struct_para_init(dma_parameter_struct* init_struct);
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/* initialize DMA channel */
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void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct);
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/* enable DMA circulation mode */
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void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
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/* disable DMA circulation mode */
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void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
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/* enable memory to memory mode */
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void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx);
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/* disable memory to memory mode */
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void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx);
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/* enable DMA channel */
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void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
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/* disable DMA channel */
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void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
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/* DMA configuration functions */
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/* set DMA peripheral base address */
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void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
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/* set DMA memory base address */
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void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
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/* set the number of remaining data to be transferred by the DMA */
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void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number);
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/* get the number of remaining data to be transferred by the DMA */
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uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
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/* configure priority level of DMA channel */
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void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
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/* configure transfer data size of memory */
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void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth);
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/* configure transfer data size of peripheral */
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void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth);
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/* enable next address increasement algorithm of memory */
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void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
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/* disable next address increasement algorithm of memory */
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void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
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/* enable next address increasement algorithm of peripheral */
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void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
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/* disable next address increasement algorithm of peripheral */
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void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
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/* configure the direction of data transfer on the channel */
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void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction);
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/* flag and interrupt functions */
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/* check DMA flag is set or not */
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FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
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/* clear the flag of a DMA channel */
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void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
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/* check DMA flag and interrupt enable bit is set or not */
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FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
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/* clear the interrupt flag of a DMA channel */
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void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
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/* enable DMA interrupt */
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void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
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/* disable DMA interrupt */
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void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
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#endif /* GD32F10X_DMA_H */
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