369 lines
26 KiB
C
369 lines
26 KiB
C
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/*!
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\file gd32f10x_adc.h
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\brief definitions for the ADC
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\version 2014-12-26, V1.0.0, firmware for GD32F10x
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\version 2017-06-20, V2.0.0, firmware for GD32F10x
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\version 2018-07-31, V2.1.0, firmware for GD32F10x
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F10x_ADC_H
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#define GD32F10x_ADC_H
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#include "gd32f10x.h"
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/* ADC definitions */
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#define ADC0 ADC_BASE
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#define ADC1 (ADC_BASE + 0x400U)
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#define ADC2 (ADC_BASE + 0x1800U)
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/* registers definitions */
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#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */
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#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */
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#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */
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#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */
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#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */
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#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */
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#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */
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#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */
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#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */
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#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */
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#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */
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#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */
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#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */
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#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */
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#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */
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#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */
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#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */
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#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */
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#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */
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#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */
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/* bits definitions */
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/* ADC_STAT */
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#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
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#define ADC_STAT_EOC BIT(1) /*!< end of conversion */
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#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */
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#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
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#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
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/* ADC_CTL0 */
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#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
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#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
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#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
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#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
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#define ADC_CTL0_SM BIT(8) /*!< scan mode */
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#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
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#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
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#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
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#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
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#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
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#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */
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#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
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#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
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#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
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/* ADC_CTL1 */
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#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
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#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
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#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
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#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
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#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
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#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
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#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */
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#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */
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#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */
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#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */
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#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */
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#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */
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#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */
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/* ADC_SAMPTx x=0..1 */
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#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */
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/* ADC_IOFFx x=0..3 */
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#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */
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/* ADC_WDHT */
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#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */
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/* ADC_WDLT */
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#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
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/* ADC_RSQx x=0..2 */
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#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */
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#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */
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/* ADC_ISQ */
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#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */
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#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
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/* ADC_IDATAx x=0..3*/
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#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */
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/* ADC_RDATA */
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#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */
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#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */
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/* constants definitions */
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/* adc_stat register value */
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#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
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#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */
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#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */
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#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */
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#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */
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/* adc_ctl0 register value */
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#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */
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/* scan mode */
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#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
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/* inserted channel group convert automatically */
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#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
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/* ADC sync mode */
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#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */
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#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */
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#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */
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#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */
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#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */
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#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */
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#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */
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#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */
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#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */
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#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */
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#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */
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/* adc_ctl1 register value */
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#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */
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#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */
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/* continuous mode */
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#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
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/* external trigger select for regular channel */
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#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */
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/* for ADC0 and ADC1 regular channel */
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#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */
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#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */
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#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */
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#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */
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#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */
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#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */
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#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< TIMER7 TRGO event select */
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#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */
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#define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */
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/* for ADC2 regular channel */
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#define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0) /*!< TIMER2 CH0 event select */
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#define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1) /*!< TIMER1 CH2 event select */
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#define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */
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#define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3) /*!< TIMER7 CH0 event select */
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#define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4) /*!< TIMER7 TRGO event select */
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#define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< TIMER4 CH0 event select */
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#define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< TIMER4 CH2 event select */
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/* external trigger mode for inserted channel */
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#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */
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/* for ADC0 and ADC1 inserted channel */
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#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
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#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
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#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */
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#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */
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#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */
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#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */
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#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */
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#define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6) /*!< TIMER7 CH3 event select */
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#define ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */
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/* for ADC2 inserted channel */
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#define ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
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#define ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
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#define ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2) /*!< TIMER3 CH2 event select */
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#define ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3) /*!< TIMER7 CH1 event select */
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#define ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4) /*!< TIMER7 CH3 event select */
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#define ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5) /*!< TIMER4 TRGO event select */
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#define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6) /*!< TIMER4 CH3 event select */
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/* adc_samptx register value */
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#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */
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#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */
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#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */
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#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */
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#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */
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#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */
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#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */
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#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */
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#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */
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/* adc_ioffx register value */
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#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */
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/* adc_wdht register value */
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#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */
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/* adc_wdlt register value */
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#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */
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/* adc_rsqx register value */
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#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */
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/* adc_isq register value */
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#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */
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/* ADC channel group definitions */
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#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */
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#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */
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#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */
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#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */
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/* ADC inserted channel definitions */
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#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */
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#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */
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#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */
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#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */
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/* ADC channel definitions */
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#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
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#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
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#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
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#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
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#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
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#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
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#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
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#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
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#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
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#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
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#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */
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#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */
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#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */
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#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */
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#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */
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#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */
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#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
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#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
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/* ADC interrupt */
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#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
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#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
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#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
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/* ADC interrupt flag */
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#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */
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#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */
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#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */
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/* function declarations */
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/* initialization config */
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/* reset ADC */
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void adc_deinit(uint32_t adc_periph);
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/* configure the ADC sync mode */
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void adc_mode_config(uint32_t mode);
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/* enable or disable ADC special function */
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void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue);
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/* configure ADC data alignment */
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void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment);
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/* enable ADC interface */
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void adc_enable(uint32_t adc_periph);
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/* disable ADC interface */
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void adc_disable(uint32_t adc_periph);
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/* ADC calibration and reset calibration */
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void adc_calibration_enable(uint32_t adc_periph);
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/* enable the temperature sensor and Vrefint channel */
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void adc_tempsensor_vrefint_enable(void);
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/* disable the temperature sensor and Vrefint channel */
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void adc_tempsensor_vrefint_disable(void);
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/* DMA config */
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/* enable DMA request */
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void adc_dma_mode_enable(uint32_t adc_periph);
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/* disable DMA request */
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void adc_dma_mode_disable(uint32_t adc_periph);
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/* regular group and inserted group config */
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/* configure ADC discontinuous mode */
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void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length);
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/* configure the length of regular channel group or inserted channel group */
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void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length);
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/* configure ADC regular channel */
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void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
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/* configure ADC inserted channel */
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void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
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/* configure ADC inserted channel offset */
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void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset);
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/* configure ADC external trigger source */
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void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source);
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/* configure ADC external trigger */
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void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue);
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/* enable ADC software trigger */
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void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group);
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/* get channel data */
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/* read ADC regular group data register */
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uint16_t adc_regular_data_read(uint32_t adc_periph);
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/* read ADC inserted group data register */
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uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel);
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/* read the last ADC0 and ADC1 conversion result data in sync mode */
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uint32_t adc_sync_mode_convert_value_read(void);
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/* watchdog config */
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/* configure ADC analog watchdog single channel */
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void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel);
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/* configure ADC analog watchdog group channel */
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void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group);
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/* disable ADC analog watchdog */
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void adc_watchdog_disable(uint32_t adc_periph);
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/* configure ADC analog watchdog threshold */
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void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold);
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/* interrupt & flag functions */
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/* get the ADC flag bits */
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FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag);
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/* clear the ADC flag bits */
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void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag);
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/* get the bit state of ADCx software start conversion */
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FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph);
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/* get the bit state of ADCx software inserted channel start conversion */
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FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph);
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/* get the ADC interrupt bits */
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FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt);
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/* clear the ADC flag */
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void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt);
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/* enable ADC interrupt */
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void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt);
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/* disable ADC interrupt */
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void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt);
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#endif /* GD32F10x_ADC_H */
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