2018-12-08 10:42:40 +08:00
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/02 Bernard The first version
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*/
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2018-12-08 17:08:52 +08:00
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#include "cpuport.h"
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2018-12-08 10:42:40 +08:00
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.section .text.entry
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.align 2
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.global trap_entry
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trap_entry:
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/* save all from thread context */
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addi sp, sp, -32 * REGBYTES
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STORE x1, 1 * REGBYTES(sp)
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li t0, 0x80
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STORE t0, 2 * REGBYTES(sp)
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STORE x4, 4 * REGBYTES(sp)
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STORE x5, 5 * REGBYTES(sp)
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STORE x6, 6 * REGBYTES(sp)
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STORE x7, 7 * REGBYTES(sp)
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STORE x8, 8 * REGBYTES(sp)
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STORE x9, 9 * REGBYTES(sp)
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STORE x10, 10 * REGBYTES(sp)
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STORE x11, 11 * REGBYTES(sp)
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STORE x12, 12 * REGBYTES(sp)
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STORE x13, 13 * REGBYTES(sp)
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STORE x14, 14 * REGBYTES(sp)
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STORE x15, 15 * REGBYTES(sp)
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STORE x16, 16 * REGBYTES(sp)
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STORE x17, 17 * REGBYTES(sp)
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STORE x18, 18 * REGBYTES(sp)
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STORE x19, 19 * REGBYTES(sp)
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STORE x20, 20 * REGBYTES(sp)
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STORE x21, 21 * REGBYTES(sp)
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STORE x22, 22 * REGBYTES(sp)
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STORE x23, 23 * REGBYTES(sp)
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STORE x24, 24 * REGBYTES(sp)
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STORE x25, 25 * REGBYTES(sp)
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STORE x26, 26 * REGBYTES(sp)
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STORE x27, 27 * REGBYTES(sp)
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STORE x28, 28 * REGBYTES(sp)
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STORE x29, 29 * REGBYTES(sp)
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STORE x30, 30 * REGBYTES(sp)
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STORE x31, 31 * REGBYTES(sp)
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/* save break thread stack to s0 */
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move s0, sp
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/* switch to interrupt stack */
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la sp, _sp
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/* interrupt handle */
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call rt_interrupt_enter
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csrr a0, mcause
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csrr a1, mepc
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mv a2, sp
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call handle_trap
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call rt_interrupt_leave
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/* switch to from_thread stack */
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move sp, s0
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/* need to switch new thread */
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la s0, rt_thread_switch_interrupt_flag
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2018-12-15 11:47:10 +08:00
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lw s2, 0(s0)
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2018-12-08 10:42:40 +08:00
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beqz s2, spurious_interrupt
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2018-12-15 11:47:10 +08:00
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sw zero, 0(s0)
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2018-12-08 10:42:40 +08:00
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csrr a0, mepc
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STORE a0, 0 * REGBYTES(sp)
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la s0, rt_interrupt_from_thread
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LOAD s1, 0(s0)
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STORE sp, 0(s1)
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la s0, rt_interrupt_to_thread
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LOAD s1, 0(s0)
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LOAD sp, 0(s1)
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LOAD a0, 0 * REGBYTES(sp)
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csrw mepc, a0
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spurious_interrupt:
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LOAD x1, 1 * REGBYTES(sp)
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/* Remain in M-mode after mret */
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li t0, 0x00001800
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csrs mstatus, t0
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LOAD t0, 2 * REGBYTES(sp)
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csrs mstatus, t0
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LOAD x4, 4 * REGBYTES(sp)
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LOAD x5, 5 * REGBYTES(sp)
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LOAD x6, 6 * REGBYTES(sp)
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LOAD x7, 7 * REGBYTES(sp)
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LOAD x8, 8 * REGBYTES(sp)
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LOAD x9, 9 * REGBYTES(sp)
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LOAD x10, 10 * REGBYTES(sp)
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LOAD x11, 11 * REGBYTES(sp)
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LOAD x12, 12 * REGBYTES(sp)
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LOAD x13, 13 * REGBYTES(sp)
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LOAD x14, 14 * REGBYTES(sp)
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LOAD x15, 15 * REGBYTES(sp)
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LOAD x16, 16 * REGBYTES(sp)
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LOAD x17, 17 * REGBYTES(sp)
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LOAD x18, 18 * REGBYTES(sp)
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LOAD x19, 19 * REGBYTES(sp)
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LOAD x20, 20 * REGBYTES(sp)
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LOAD x21, 21 * REGBYTES(sp)
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LOAD x22, 22 * REGBYTES(sp)
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LOAD x23, 23 * REGBYTES(sp)
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LOAD x24, 24 * REGBYTES(sp)
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LOAD x25, 25 * REGBYTES(sp)
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LOAD x26, 26 * REGBYTES(sp)
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LOAD x27, 27 * REGBYTES(sp)
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LOAD x28, 28 * REGBYTES(sp)
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LOAD x29, 29 * REGBYTES(sp)
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LOAD x30, 30 * REGBYTES(sp)
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LOAD x31, 31 * REGBYTES(sp)
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addi sp, sp, 32 * REGBYTES
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mret
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