rt-thread/bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_timr.c

442 lines
16 KiB
C
Raw Normal View History

2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
2021-05-06 10:10:29 +08:00
* : SWM320_timr.c
2021-09-13 21:04:42 +08:00
* : SWM320单片机的计数器/
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
2021-05-06 10:10:29 +08:00
* :
2021-09-13 21:04:42 +08:00
* : V1.1.0 20171025
* :
2021-02-18 13:29:12 +08:00
*
*
*******************************************************************************************************************************************
* @attention
*
2021-09-13 21:04:42 +08:00
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
2021-02-18 13:29:12 +08:00
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
2021-09-13 21:04:42 +08:00
* COPYRIGHT 2012 Synwit Technology
2021-02-18 13:29:12 +08:00
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_timr.h"
2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
2021-05-06 10:10:29 +08:00
* : TIMR_Init()
2021-09-13 21:04:42 +08:00
* : TIMR定时器/
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* uint32_t mode TIMR_MODE_TIMER TIMR_MODE_COUNTER
* uint32_t period /
* uint32_t int_en 使
2021-05-06 10:10:29 +08:00
* :
* :
2021-02-18 13:29:12 +08:00
******************************************************************************************************************************************/
2021-05-06 10:42:41 +08:00
void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int_en)
2021-02-18 13:29:12 +08:00
{
2021-05-06 10:42:41 +08:00
SYS->CLKEN |= (0x01 << SYS_CLKEN_TIMR_Pos);
TIMR_Stop(TIMRx); //一些关键寄存器只能在定时器停止时设置
TIMRx->CTRL &= ~TIMR_CTRL_CLKSRC_Msk;
TIMRx->CTRL |= mode << TIMR_CTRL_CLKSRC_Pos;
TIMRx->LDVAL = period;
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->IF = (1 << TIMRG_IF_TIMR0_Pos); //使能中断前清除中断标志
TIMRG->IE &= ~TIMRG_IE_TIMR0_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR0_Pos);
if (int_en)
NVIC_EnableIRQ(TIMR0_IRQn);
break;
case ((uint32_t)TIMR1):
TIMRG->IF = (1 << TIMRG_IF_TIMR1_Pos);
TIMRG->IE &= ~TIMRG_IE_TIMR1_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR1_Pos);
if (int_en)
NVIC_EnableIRQ(TIMR1_IRQn);
break;
case ((uint32_t)TIMR2):
TIMRG->IF = (1 << TIMRG_IF_TIMR2_Pos);
TIMRG->IE &= ~TIMRG_IE_TIMR2_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR2_Pos);
if (int_en)
NVIC_EnableIRQ(TIMR2_IRQn);
break;
case ((uint32_t)TIMR3):
TIMRG->IF = (1 << TIMRG_IF_TIMR3_Pos);
TIMRG->IE &= ~TIMRG_IE_TIMR3_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR3_Pos);
if (int_en)
NVIC_EnableIRQ(TIMR3_IRQn);
break;
case ((uint32_t)TIMR4):
TIMRG->IF = (1 << TIMRG_IF_TIMR4_Pos);
TIMRG->IE &= ~TIMRG_IE_TIMR4_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR4_Pos);
if (int_en)
NVIC_EnableIRQ(TIMR4_IRQn);
break;
case ((uint32_t)TIMR5):
TIMRG->IF = (1 << TIMRG_IF_TIMR5_Pos);
TIMRG->IE &= ~TIMRG_IE_TIMR5_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR5_Pos);
if (int_en)
NVIC_EnableIRQ(TIMR5_IRQn);
break;
}
2021-02-18 13:29:12 +08:00
}
2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
* : TIMR_Start()
* : /
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
2021-05-06 10:10:29 +08:00
* :
* :
2021-02-18 13:29:12 +08:00
******************************************************************************************************************************************/
2021-05-06 10:42:41 +08:00
void TIMR_Start(TIMR_TypeDef *TIMRx)
2021-02-18 13:29:12 +08:00
{
2021-05-06 10:42:41 +08:00
TIMRx->CTRL |= TIMR_CTRL_EN_Msk;
2021-02-18 13:29:12 +08:00
}
2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
* : TIMR_Stop()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
2021-05-06 10:10:29 +08:00
* :
* :
2021-02-18 13:29:12 +08:00
******************************************************************************************************************************************/
2021-05-06 10:42:41 +08:00
void TIMR_Stop(TIMR_TypeDef *TIMRx)
2021-02-18 13:29:12 +08:00
{
2021-05-06 10:42:41 +08:00
TIMRx->CTRL &= ~TIMR_CTRL_EN_Msk;
2021-02-18 13:29:12 +08:00
}
2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
* : TIMR_Halt()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
2021-05-06 10:10:29 +08:00
* :
* :
2021-02-18 13:29:12 +08:00
******************************************************************************************************************************************/
2021-05-06 10:42:41 +08:00
void TIMR_Halt(TIMR_TypeDef *TIMRx)
2021-02-18 13:29:12 +08:00
{
2021-05-06 10:42:41 +08:00
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR0_Pos);
break;
case ((uint32_t)TIMR1):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR1_Pos);
break;
case ((uint32_t)TIMR2):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR2_Pos);
break;
case ((uint32_t)TIMR3):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR3_Pos);
break;
case ((uint32_t)TIMR4):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR4_Pos);
break;
case ((uint32_t)TIMR5):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR5_Pos);
break;
}
2021-02-18 13:29:12 +08:00
}
2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
* : TIMR_Resume()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
2021-05-06 10:10:29 +08:00
* :
* :
2021-02-18 13:29:12 +08:00
******************************************************************************************************************************************/
2021-05-06 10:42:41 +08:00
void TIMR_Resume(TIMR_TypeDef *TIMRx)
2021-02-18 13:29:12 +08:00
{
2021-05-06 10:42:41 +08:00
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR0_Pos);
break;
case ((uint32_t)TIMR1):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR1_Pos);
break;
case ((uint32_t)TIMR2):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR2_Pos);
break;
case ((uint32_t)TIMR3):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR3_Pos);
break;
case ((uint32_t)TIMR4):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR4_Pos);
break;
case ((uint32_t)TIMR5):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR5_Pos);
break;
}
2021-02-18 13:29:12 +08:00
}
2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
2021-05-06 10:10:29 +08:00
* : TIMR_SetPeriod()
2021-09-13 21:04:42 +08:00
* : /
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* uint32_t period /
2021-05-06 10:10:29 +08:00
* :
* :
2021-02-18 13:29:12 +08:00
******************************************************************************************************************************************/
2021-05-06 10:42:41 +08:00
void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period)
2021-02-18 13:29:12 +08:00
{
2021-05-06 10:42:41 +08:00
TIMRx->LDVAL = period;
2021-02-18 13:29:12 +08:00
}
2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
2021-05-06 10:10:29 +08:00
* : TIMR_GetPeriod()
2021-09-13 21:04:42 +08:00
* : /
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* : uint32_t /
2021-05-06 10:10:29 +08:00
* :
2021-02-18 13:29:12 +08:00
******************************************************************************************************************************************/
2021-05-06 10:42:41 +08:00
uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx)
2021-02-18 13:29:12 +08:00
{
2021-05-06 10:42:41 +08:00
return TIMRx->LDVAL;
2021-02-18 13:29:12 +08:00
}
2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
* : TIMR_GetCurValue()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* : uint32_t
2021-05-06 10:10:29 +08:00
* :
2021-02-18 13:29:12 +08:00
******************************************************************************************************************************************/
2021-05-06 10:42:41 +08:00
uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx)
2021-02-18 13:29:12 +08:00
{
2021-05-06 10:42:41 +08:00
return TIMRx->CVAL;
2021-02-18 13:29:12 +08:00
}
2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
* : TIMR_INTEn()
* : 使
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
2021-05-06 10:10:29 +08:00
* :
* :
2021-02-18 13:29:12 +08:00
******************************************************************************************************************************************/
2021-05-06 10:42:41 +08:00
void TIMR_INTEn(TIMR_TypeDef *TIMRx)
2021-02-18 13:29:12 +08:00
{
2021-05-06 10:42:41 +08:00
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR0_Pos);
NVIC_EnableIRQ(TIMR0_IRQn);
break;
case ((uint32_t)TIMR1):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR1_Pos);
NVIC_EnableIRQ(TIMR1_IRQn);
break;
case ((uint32_t)TIMR2):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR2_Pos);
NVIC_EnableIRQ(TIMR2_IRQn);
break;
case ((uint32_t)TIMR3):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR3_Pos);
NVIC_EnableIRQ(TIMR3_IRQn);
break;
case ((uint32_t)TIMR4):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR4_Pos);
NVIC_EnableIRQ(TIMR4_IRQn);
break;
case ((uint32_t)TIMR5):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR5_Pos);
NVIC_EnableIRQ(TIMR5_IRQn);
break;
}
2021-02-18 13:29:12 +08:00
}
2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
2021-05-06 10:10:29 +08:00
* : TIMR_INTDis()
2021-09-13 21:04:42 +08:00
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
2021-05-06 10:10:29 +08:00
* :
* :
2021-02-18 13:29:12 +08:00
******************************************************************************************************************************************/
2021-05-06 10:42:41 +08:00
void TIMR_INTDis(TIMR_TypeDef *TIMRx)
2021-02-18 13:29:12 +08:00
{
2021-05-06 10:42:41 +08:00
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR0_Pos);
break;
case ((uint32_t)TIMR1):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR1_Pos);
break;
case ((uint32_t)TIMR2):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR2_Pos);
break;
case ((uint32_t)TIMR3):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR3_Pos);
break;
case ((uint32_t)TIMR4):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR4_Pos);
break;
case ((uint32_t)TIMR5):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR5_Pos);
break;
}
2021-02-18 13:29:12 +08:00
}
2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
* : TIMR_INTClr()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
2021-05-06 10:10:29 +08:00
* :
* :
2021-02-18 13:29:12 +08:00
******************************************************************************************************************************************/
2021-05-06 10:42:41 +08:00
void TIMR_INTClr(TIMR_TypeDef *TIMRx)
2021-02-18 13:29:12 +08:00
{
2021-05-06 10:42:41 +08:00
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR0_Pos);
break;
case ((uint32_t)TIMR1):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR1_Pos);
break;
case ((uint32_t)TIMR2):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR2_Pos);
break;
case ((uint32_t)TIMR3):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR3_Pos);
break;
case ((uint32_t)TIMR4):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR4_Pos);
break;
case ((uint32_t)TIMR5):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR5_Pos);
break;
}
2021-02-18 13:29:12 +08:00
}
2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
2021-05-06 10:10:29 +08:00
* : TIMR_INTStat()
2021-09-13 21:04:42 +08:00
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* : uint32_t 0 TIMRx未产生中断 1 TIMRx产生了中断
2021-05-06 10:10:29 +08:00
* :
2021-02-18 13:29:12 +08:00
******************************************************************************************************************************************/
2021-05-06 10:42:41 +08:00
uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx)
2021-02-18 13:29:12 +08:00
{
2021-05-06 10:42:41 +08:00
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
return (TIMRG->IF & TIMRG_IF_TIMR0_Msk) ? 1 : 0;
case ((uint32_t)TIMR1):
return (TIMRG->IF & TIMRG_IF_TIMR1_Msk) ? 1 : 0;
case ((uint32_t)TIMR2):
return (TIMRG->IF & TIMRG_IF_TIMR2_Msk) ? 1 : 0;
case ((uint32_t)TIMR3):
return (TIMRG->IF & TIMRG_IF_TIMR3_Msk) ? 1 : 0;
2021-02-18 13:29:12 +08:00
2021-05-06 10:42:41 +08:00
case ((uint32_t)TIMR4):
return (TIMRG->IF & TIMRG_IF_TIMR4_Msk) ? 1 : 0;
case ((uint32_t)TIMR5):
return (TIMRG->IF & TIMRG_IF_TIMR5_Msk) ? 1 : 0;
}
return 0;
}
2021-02-18 13:29:12 +08:00
2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
2021-05-06 10:10:29 +08:00
* : Pulse_Init()
2021-09-13 21:04:42 +08:00
* :
* : uint32_t pulse PULSE_LOW PULSE_HIGH
* uint32_t int_en 使
2021-05-06 10:10:29 +08:00
* :
* :
2021-02-18 13:29:12 +08:00
******************************************************************************************************************************************/
void Pulse_Init(uint32_t pulse, uint32_t int_en)
2021-05-06 10:42:41 +08:00
{
SYS->CLKEN |= (0x01 << SYS_CLKEN_TIMR_Pos);
TIMRG->PCTRL = (0 << TIMRG_PCTRL_CLKSRC_Pos) | // 系统时钟作为时钟源
(pulse << TIMRG_PCTRL_HIGH_Pos) |
(0 << TIMRG_PCTRL_EN_Pos);
TIMRG->IE |= (1 << TIMRG_IE_PULSE_Pos); //使能才能查询中断标志
if (int_en)
NVIC_EnableIRQ(PULSE_IRQn);
2021-02-18 13:29:12 +08:00
}
2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
2021-05-06 10:10:29 +08:00
* : Pulse_Start()
2021-09-13 21:04:42 +08:00
* :
2021-05-06 10:10:29 +08:00
* :
* :
* :
2021-02-18 13:29:12 +08:00
******************************************************************************************************************************************/
void Pulse_Start(void)
2021-05-06 10:42:41 +08:00
{
TIMRG->PCTRL |= (1 << TIMRG_PCTRL_EN_Pos);
2021-02-18 13:29:12 +08:00
}
2021-09-13 21:04:42 +08:00
/******************************************************************************************************************************************
2021-05-06 10:10:29 +08:00
* : Pulse_Done()
2021-09-13 21:04:42 +08:00
* :
2021-05-06 10:10:29 +08:00
* :
2021-09-13 21:04:42 +08:00
* : uint32_t 1 0
2021-05-06 10:10:29 +08:00
* :
2021-02-18 13:29:12 +08:00
******************************************************************************************************************************************/
uint32_t Pulse_Done(void)
{
2021-05-06 10:42:41 +08:00
if (TIMRG->IF & TIMRG_IF_PULSE_Msk)
{
TIMRG->IF = TIMRG_IF_PULSE_Msk; // 清除中断标志
return 1;
}
else
{
return 0;
}
2021-02-18 13:29:12 +08:00
}