289 lines
8.8 KiB
C
289 lines
8.8 KiB
C
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/******************************************************************************
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* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file mpu.c
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*
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* This file contains initial configuration of the MPU.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- ---------------------------------------------------
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* 5.00 pkp 02/20/14 First release
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* 5.04 pkp 12/18/15 Updated MPU initialization as per the proper address map
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* 6.00 pkp 06/27/16 moving the Init_MPU code to .boot section since it is a
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* part of processor boot process
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* 6.2 mus 01/27/17 Updated to support IAR compiler
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* 7.1 mus 09/11/19 Added warning message if DDR size is not in power of 2.
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* Fix for CR#1038577.
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* 7.2 asa 04/08/20 Fix warning in the function Init_MPU.
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* </pre>
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*
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* @note
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*
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* None.
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include <rtthread.h>
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#include "zynqmp-r5.h"
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#include "xreg_cortexr5.h"
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#include "xpseudo_asm_gcc.h"
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/***************** Macros (Inline Functions) Definitions *********************/
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/**************************** Type Definitions *******************************/
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typedef rt_int32_t s32;
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typedef rt_uint64_t u64;
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typedef rt_uint32_t u32;
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/************************** Constant Definitions *****************************/
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/************************** Variable Definitions *****************************/
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static const struct {
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u64 size;
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unsigned int encoding;
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}region_size[] = {
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{ 0x20, REGION_32B },
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{ 0x40, REGION_64B },
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{ 0x80, REGION_128B },
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{ 0x100, REGION_256B },
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{ 0x200, REGION_512B },
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{ 0x400, REGION_1K },
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{ 0x800, REGION_2K },
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{ 0x1000, REGION_4K },
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{ 0x2000, REGION_8K },
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{ 0x4000, REGION_16K },
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{ 0x8000, REGION_32K },
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{ 0x10000, REGION_64K },
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{ 0x20000, REGION_128K },
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{ 0x40000, REGION_256K },
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{ 0x80000, REGION_512K },
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{ 0x100000, REGION_1M },
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{ 0x200000, REGION_2M },
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{ 0x400000, REGION_4M },
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{ 0x800000, REGION_8M },
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{ 0x1000000, REGION_16M },
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{ 0x2000000, REGION_32M },
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{ 0x4000000, REGION_64M },
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{ 0x8000000, REGION_128M },
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{ 0x10000000, REGION_256M },
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{ 0x20000000, REGION_512M },
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{ 0x40000000, REGION_1G },
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{ 0x80000000, REGION_2G },
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{ 0x100000000, REGION_4G },
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};
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/************************** Function Prototypes ******************************/
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#if defined (__GNUC__)
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void Init_MPU(void) __attribute__((__section__(".boot")));
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static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) __attribute__((__section__(".boot")));
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static void Xil_DisableMPURegions(void) __attribute__((__section__(".boot")));
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#elif defined (__ICCARM__)
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#pragma default_function_attributes = @ ".boot"
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void Init_MPU(void);
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static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib);
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static void Xil_DisableMPURegions(void);
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#endif
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/*****************************************************************************
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*
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* Initialize MPU for a given address map and Enabled the background Region in
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* MPU with default memory attributes for rest of address range for Cortex R5
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* processor.
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*
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* @param None.
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*
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* @return None.
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*
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*
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******************************************************************************/
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void Init_MPU(void)
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{
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u32 Addr;
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u32 RegSize = 0U;
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u32 Attrib;
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u32 RegNum = 0, i, Offset = 0;
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u64 size;
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Xil_DisableMPURegions();
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Addr = 0x00000000U;
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#ifdef XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR
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/* If the DDR is present, configure region as per DDR size */
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size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1;
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if (size < 0x80000000) {
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/* Lookup the size. */
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for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
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if (size <= region_size[i].size) {
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RegSize = region_size[i].encoding;
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/* Check if DDR size is in power of 2*/
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if ( XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR == 0x100000)
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Offset = XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR;
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if (region_size[i].size > (size + Offset + 1)) {
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rt_kprintf ("WARNING: DDR size mapped to Cortexr5 processor is not \
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in power of 2. As processor allocates MPU regions size \
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in power of 2, address range %llx to %x has been \
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incorrectly mapped as normal memory \n", \
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region_size[i].size - 1, ((u32)XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR + 1));
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}
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break;
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}
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}
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} else {
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/* if the DDR size is > 2GB, truncate it to 2GB */
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RegSize = REGION_2G;
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}
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#else
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/* For DDRless system, configure region for TCM */
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RegSize = REGION_256K;
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#endif
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Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
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Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
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RegNum++;
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/*
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* 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL.
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* 512 MB - LPD-PL interface
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* 256 MB - FPD-PL (HPM0) interface
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* 256 MB - FPD-PL (HPM1) interface
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*/
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Addr = 0x80000000;
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RegSize = REGION_1G;
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Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ;
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Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
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RegNum++;
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/* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */
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Addr = 0xC0000000U;
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RegSize = REGION_512M;
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Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
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Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
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RegNum++;
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/* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */
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Addr = 0xE0000000U;
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RegSize = REGION_256M;
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Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
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Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
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RegNum++;
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/* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */
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Addr = 0xF8000000U;
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RegSize = REGION_16M;
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Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
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Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
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RegNum++;
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/* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */
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Addr = 0xF9000000U;
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RegSize = REGION_1M;
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Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
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Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
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RegNum++;
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/* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */
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Addr = 0xFD000000U;
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RegSize = REGION_16M;
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Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
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Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
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RegNum++;
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/* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */
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Addr = 0xFE000000U;
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RegSize = REGION_16M;
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Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
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Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
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RegNum++;
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/*
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* 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves,
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* CSU, PMU, TCM, OCM
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*/
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Addr = 0xFF000000U;
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RegSize = REGION_16M;
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Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
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Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
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RegNum++;
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/* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */
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Addr = 0xFFFC0000U;
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RegSize = REGION_256K;
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Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ;
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Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
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/* A total of 10 MPU regions are allocated with another 6 being free for users */
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}
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/*****************************************************************************
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*
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* Set the memory attributes for a section of memory with starting address addr
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* of the region size defined by reg_size having attributes attrib of region number
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* reg_num
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*
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* @param addr is the address for which attributes are to be set.
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* @param attrib specifies the attributes for that memory region.
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* @param reg_size specifies the size for that memory region.
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* @param reg_num specifies the number for that memory region.
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* @return None.
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*
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*
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******************************************************************************/
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static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib)
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{
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u32 Local_reg_size = reg_size;
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Local_reg_size = Local_reg_size<<1U;
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Local_reg_size |= REGION_EN;
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dsb();
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mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
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isb();
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mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */
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mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */
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mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/
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dsb();
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isb(); /* synchronize context on this processor */
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}
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/*****************************************************************************
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*
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* Disable all the MPU regions if any of them is enabled
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*
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* @param None.
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*
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* @return None.
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*
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*
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******************************************************************************/
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static void Xil_DisableMPURegions(void)
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{
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u32 Temp = 0U;
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u32 Index = 0U;
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for (Index = 0; Index <= 15; Index++) {
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mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index);
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#if defined (__GNUC__)
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Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
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#endif
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Temp &= (~REGION_EN);
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dsb();
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mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
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dsb();
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isb();
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}
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}
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#if defined (__ICCARM__)
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#pragma default_function_attributes =
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#endif
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