2020-05-25 17:30:05 +08:00
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#ifndef __RASPI4_H__
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#define __RASPI4_H__
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//https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/rpi_DATA_2711_1p0.pdf
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#define __REG32(x) (*((volatile unsigned int *)(x)))
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#define __REG16(x) (*((volatile unsigned short *)(x)))
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/* GIC IRQ MAX */
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#define MAX_HANDLERS (256)
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/* base address */
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#define PER_BASE (0xFE000000)
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2020-05-26 13:34:02 +08:00
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//gpio offset
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#define GPIO_BASE_OFFSET (0x00200000)
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//pl011 offset
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#define PL011_UART0_BASE_OFFSET (0x00201000)
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#define PL011_UART2_BASE_OFFSET (0x00201400)
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#define PL011_UART3_BASE_OFFSET (0x00201600)
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#define PL011_UART4_BASE_OFFSET (0x00201800)
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#define PL011_UART5_BASE_OFFSET (0x00201A00)
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//pactl cs offset
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#define PACTL_CS_OFFSET (0x00204E00)
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//aux offset
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#define AUX_BASE_OFFSET (0x00215000)
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2020-05-25 17:30:05 +08:00
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/* GPIO */
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2020-05-26 13:34:02 +08:00
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#define GPIO_BASE (PER_BASE + GPIO_BASE_OFFSET)
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2020-05-25 17:30:05 +08:00
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/* Timer (ARM side) */
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#define ARM_TIMER_IRQ (64)
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#define ARM_TIMER_BASE (PER_BASE + 0xB000)
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#define ARM_TIMER_LOAD HWREG32(ARM_TIMER_BASE + 0x400)
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#define ARM_TIMER_VALUE HWREG32(ARM_TIMER_BASE + 0x404)
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#define ARM_TIMER_CTRL HWREG32(ARM_TIMER_BASE + 0x408)
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#define ARM_TIMER_IRQCLR HWREG32(ARM_TIMER_BASE + 0x40C)
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#define ARM_TIMER_RAWIRQ HWREG32(ARM_TIMER_BASE + 0x410)
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#define ARM_TIMER_MASKIRQ HWREG32(ARM_TIMER_BASE + 0x414)
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#define ARM_TIMER_RELOAD HWREG32(ARM_TIMER_BASE + 0x418)
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#define ARM_TIMER_PREDIV HWREG32(ARM_TIMER_BASE + 0x41C)
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#define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420)
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/* UART PL011 */
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2020-05-26 13:34:02 +08:00
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#define UART0_BASE (PER_BASE + PL011_UART0_BASE_OFFSET)
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#define UART2_BASE (PER_BASE + PL011_UART2_BASE_OFFSET)
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#define UART3_BASE (PER_BASE + PL011_UART3_BASE_OFFSET)
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#define UART4_BASE (PER_BASE + PL011_UART4_BASE_OFFSET)
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#define UART5_BASE (PER_BASE + PL011_UART5_BASE_OFFSET)
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#define IRQ_AUX_UART (96 + 29)
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2020-05-25 17:30:05 +08:00
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#define UART_REFERENCE_CLOCK (48000000)
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2020-05-26 13:34:02 +08:00
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/* AUX */
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#define AUX_BASE (PER_BASE + AUX_BASE_OFFSET)
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#define IRQ_PL011 (96 + 57)
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/* Peripheral IRQ OR-ing */
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#define PACTL_CS HWREG32((PER_BASE + PACTL_CS_OFFSET))
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typedef enum {
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IRQ_SPI0 = 0x00000000,
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IRQ_SPI1 = 0x00000002,
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IRQ_SPI2 = 0x00000004,
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IRQ_SPI3 = 0x00000008,
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IRQ_SPI4 = 0x00000010,
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IRQ_SPI5 = 0x00000020,
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IRQ_SPI6 = 0x00000040,
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IRQ_I2C0 = 0x00000100,
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IRQ_I2C1 = 0x00000200,
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IRQ_I2C2 = 0x00000400,
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IRQ_I2C3 = 0x00000800,
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IRQ_I2C4 = 0x00001000,
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IRQ_I2C5 = 0x00002000,
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IRQ_I2C6 = 0x00004000,
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IRQ_I2C7 = 0x00008000,
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IRQ_UART5 = 0x00010000,
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IRQ_UART4 = 0x00020000,
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IRQ_UART3 = 0x00040000,
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IRQ_UART2 = 0x00080000,
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IRQ_UART0 = 0x00100000
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} PACTL_CS_VAL;
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2020-05-25 17:30:05 +08:00
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// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
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#define CORE0_TIMER_IRQ_CTRL HWREG32(0xFF800040)
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#define TIMER_IRQ 30
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#define NON_SECURE_TIMER_IRQ (1 << 1)
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/* GIC */
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#define INTC_BASE (0xff800000)
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#define ARM_GIC_NR_IRQS (512)
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#define ARM_GIC_MAX_NR (512)
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#define GIC_V2_DISTRIBUTOR_BASE (INTC_BASE + 0x00041000)
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#define GIC_V2_CPU_INTERFACE_BASE (INTC_BASE + 0x00042000)
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#define GIC_V2_HYPERVISOR_BASE (INTC_BASE + 0x00044000)
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#define GIC_V2_VIRTUAL_CPU_BASE (INTC_BASE + 0x00046000)
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#define GIC_PL400_DISTRIBUTOR_PPTR GIC_V2_DISTRIBUTOR_BASE
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#define GIC_PL400_CONTROLLER_PPTR GIC_V2_CPU_INTERFACE_BASE
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#define GIC_IRQ_START 0
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#define GIC_ACK_INTID_MASK 0x000003ff
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/* the basic constants and interfaces needed by gic */
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rt_inline rt_uint32_t platform_get_gic_dist_base(void)
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{
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return GIC_PL400_DISTRIBUTOR_PPTR;
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}
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rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
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{
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return GIC_PL400_CONTROLLER_PPTR;
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}
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static inline void __DSB(void)
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{
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__asm__ volatile ("dsb 0xF":::"memory");
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}
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#endif
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