731 lines
21 KiB
C
731 lines
21 KiB
C
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/*!
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\file gd32f4xx_i2c.c
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\brief I2C driver
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*/
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/*
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Copyright (C) 2016 GigaDevice
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2016-08-15, V1.0.0, firmware for GD32F4xx
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*/
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#include "gd32f4xx_i2c.h"
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#define I2CCLK_MAX 0x3fU /*!< i2cclk max value */
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#define I2C_STATE_MASK 0x0000FFFFU /*!< i2c state mask */
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/*!
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\brief reset I2C
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[out] none
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\retval none
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*/
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void i2c_deinit(uint32_t i2c_periph)
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{
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switch(i2c_periph){
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case I2C0:
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rcu_periph_reset_enable(RCU_I2C0RST);
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rcu_periph_reset_disable(RCU_I2C0RST);
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break;
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case I2C1:
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rcu_periph_reset_enable(RCU_I2C1RST);
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rcu_periph_reset_disable(RCU_I2C1RST);
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break;
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case I2C2:
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rcu_periph_reset_enable(RCU_I2C2RST);
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rcu_periph_reset_disable(RCU_I2C2RST);
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break;
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default:
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break;
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}
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}
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/*!
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\brief I2C clock configure
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[in] clkspeed: i2c clock speed
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\param[in] dutycyc: duty cycle in fast mode
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\arg I2C_DTCY_2: T_low/T_high=2
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\arg I2C_DTCY_16_9: T_low/T_high=16/9
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\param[out] none
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\retval none
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*/
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void i2c_clock_config(uint32_t i2c_periph,uint32_t clkspeed,uint32_t dutycyc)
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{
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uint32_t pclk1,clkc,i2cclk,risetime;
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pclk1 = rcu_clock_freq_get(CK_APB1);
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/* I2C Peripheral clock frequency */
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i2cclk=((pclk1)/(uint32_t)(1000000));
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if(i2cclk >= I2CCLK_MAX){
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i2cclk = I2CCLK_MAX;
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}
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I2C_CTL1(i2c_periph) |= (I2C_CTL1_I2CCLK & i2cclk) ;
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if(100000U >= clkspeed){
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/* standard mode the maximum SCL rise time in standard mode is 1000ns */
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risetime = (uint32_t)((pclk1/1000000U)+1U);
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if(risetime >= I2CCLK_MAX){
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I2C_RT(i2c_periph) |= I2CCLK_MAX;
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}else{
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I2C_RT(i2c_periph) |= (uint32_t)((pclk1/1000000U)+1U);
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}
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clkc = (uint32_t)(pclk1/(clkspeed*2U));
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if(clkc < 0x04U){
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/* The CLKC in standard mode minmum value is 4*/
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clkc = 0x04U;
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}
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I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc);
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}else{
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/* fast mode the maximum SCL rise time in standard mode is 300ns */
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I2C_RT(i2c_periph) |= (uint16_t)(((i2cclk*(uint16_t)300)/(uint16_t)1000)+(uint16_t)1);
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if(I2C_DTCY_2 == dutycyc){
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/* I2C_DutyCycle == 2 */
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clkc = (uint16_t)(pclk1/(clkspeed*3U));
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} else{
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/* I2C_DutyCycle == 16/9 */
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clkc = (uint16_t)(pclk1/(clkspeed*25U));
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I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
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}
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if((clkc & I2C_CKCFG_CLKC) == 0U){
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/* The CLKC in standard mode minmum value is 1*/
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clkc |= (uint16_t)0x0001;
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}
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I2C_CKCFG(i2c_periph) |= clkc;
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}
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}
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/*!
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\brief I2C address configure
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[in] i2cmod:
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\arg I2C_I2CMODE_ENABLE: I2C mode
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\arg I2C_SMBUSMODE_ENABLE: SMBus mode
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\param[in] addformat: 7bits or 10bits
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\arg I2C_ADDFORMAT_7BITS: 7bits
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\arg I2C_ADDFORMAT_10BITS: 10bits
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\param[in] addr: I2C address
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\param[out] none
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\retval none
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*/
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void i2c_mode_addr_config(uint32_t i2c_periph,uint32_t i2cmod,uint32_t addformat,uint32_t addr)
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{
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/* SMBus/I2C mode selected */
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uint32_t ctl = 0U;
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ctl = I2C_CTL0(i2c_periph);
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ctl &= ~(I2C_CTL0_SMBEN);
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ctl |= i2cmod;
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I2C_CTL0(i2c_periph) = ctl;
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/* configure address */
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I2C_SADDR0(i2c_periph) = (addformat|addr);
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}
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/*!
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\brief SMBus type selection
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[in] ack:
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\arg I2C_SMBUS_DEVICE: device
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\arg I2C_SMBUS_HOST: host
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\param[out] none
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\retval none
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*/
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void i2c_smbus_type_config(uint32_t i2c_periph,uint32_t type)
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{
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if(I2C_SMBUS_HOST == type){
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I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL;
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}else{
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I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL);
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}
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}
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/*!
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\brief whether or not to send an ACK
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[in] ack:
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\arg I2C_ACK_ENABLE: ACK will be sent
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\arg I2C_ACK_DISABLE: ACK will not be sent
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\param[out] none
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\retval none
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*/
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void i2c_ack_config(uint32_t i2c_periph,uint8_t ack)
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{
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if(I2C_ACK_ENABLE == ack){
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I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN;
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}else{
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I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN);
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}
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}
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/*!
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\brief I2C POAP position configure
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[in] pos:
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\arg I2C_ACK_ENABLE: ACK will be sent
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\arg I2C_ACK_DISABLE: ACK will not be sent
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\param[out] none
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\retval none
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*/
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void i2c_ackpos_config(uint32_t i2c_periph,uint8_t pos)
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{
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/* configure i2c POAP position */
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if(I2C_ACKPOS_NEXT == pos){
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I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP;
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}else{
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I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP);
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}
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}
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/*!
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\brief master send slave address
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[in] addr: slave address
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\param[in] trandirection: transmitter or receiver
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\arg I2C_TRANSMITTER: transmitter
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\arg I2C_RECEIVER: receiver
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\param[out] none
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\retval none
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*/
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void i2c_master_addressing(uint32_t i2c_periph,uint8_t addr,uint32_t trandirection)
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{
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if(I2C_TRANSMITTER==trandirection){
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addr = (uint8_t)((uint32_t)addr & I2C_TRANSMITTER);
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}else{
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addr = (uint8_t)((uint32_t)addr|I2C_RECEIVER);
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}
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I2C_DATA(i2c_periph) = addr;
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}
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/*!
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\brief dual-address mode switch
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[in] dualaddr:
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\arg I2C_DUADEN_DISABLE: dual-address mode disabled
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\arg I2C_DUADEN_ENABLE: dual-address mode enabled
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\param[out] none
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\retval none
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*/
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void i2c_dualaddr_enable(uint32_t i2c_periph,uint8_t dualaddr)
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{
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if(I2C_DUADEN_ENABLE == dualaddr){
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I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN;
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}else{
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I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN);
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}
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}
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/*!
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\brief enable i2c
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[out] none
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\retval none
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*/
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void i2c_enable(uint32_t i2c_periph)
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{
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I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN;
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}
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/*!
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\brief disable i2c
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[out] none
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\retval none
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*/
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void i2c_disable(uint32_t i2c_periph)
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{
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I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN);
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}
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/*!
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\brief generate a START condition on I2C bus
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[out] none
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\retval none
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*/
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void i2c_start_on_bus(uint32_t i2c_periph)
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{
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I2C_CTL0(i2c_periph) |= I2C_CTL0_START;
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}
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/*!
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\brief generate a STOP condition on I2C bus
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[out] none
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\retval none
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*/
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void i2c_stop_on_bus(uint32_t i2c_periph)
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{
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I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP;
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}
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/*!
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\brief i2c transmit data function
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[in] data: data of transmission
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\param[out] none
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\retval none
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*/
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void i2c_transmit_data(uint32_t i2c_periph,uint8_t data)
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{
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I2C_DATA(i2c_periph) = data;
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}
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/*!
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\brief i2c receive data function
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[out] none
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\retval data of received
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*/
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uint8_t i2c_receive_data(uint32_t i2c_periph)
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{
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return (uint8_t)I2C_DATA(i2c_periph);
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}
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/*!
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\brief I2C DMA mode enable
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[in] dmastste:
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\arg I2C_DMA_ON: DMA mode enabled
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\arg I2C_DMA_OFF: DMA mode disabled
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\param[out] none
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\retval none
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*/
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void i2c_dma_enable(uint32_t i2c_periph,uint32_t dmastste)
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{
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/* configure i2c DMA function */
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uint32_t ctl = 0U;
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ctl = I2C_CTL1(i2c_periph);
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ctl &= ~(I2C_CTL1_DMAON);
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ctl |= dmastste;
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I2C_CTL1(i2c_periph) = ctl;
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}
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/*!
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\brief flag indicating DMA last transfer
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\param[in] i2c_periph: I2Cx(x=0,1,2)
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\param[in] dmastste:
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\arg I2C_DMALST_ON: next DMA EOT is the last transfer
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\arg I2C_DMALST_OFF: next DMA EOT is not the last transfer
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\param[out] none
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\retval none
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*/
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void i2c_dma_last_transfer_enable(uint32_t i2c_periph,uint32_t dmalast)
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{
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/* configure DMA last transfer */
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uint32_t ctl = 0U;
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ctl = I2C_CTL1(i2c_periph);
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ctl &= ~(I2C_CTL1_DMALST);
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ctl |= dmalast;
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I2C_CTL1(i2c_periph) = ctl;
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}
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/*!
|
||
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\brief whether to stretch SCL low when data is not ready in slave mode
|
||
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\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] stretchpara:
|
||
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\arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled
|
||
|
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\arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled
|
||
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\param[out] none
|
||
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\retval none
|
||
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*/
|
||
|
|
void i2c_stretch_scl_low_config(uint32_t i2c_periph,uint32_t stretchpara)
|
||
|
|
{
|
||
|
|
/* configure I2C SCL strerching enable or disable */
|
||
|
|
uint32_t ctl = 0U;
|
||
|
|
ctl = I2C_CTL0(i2c_periph);
|
||
|
|
ctl &= ~(I2C_CTL0_DISSTRC);
|
||
|
|
ctl |= stretchpara;
|
||
|
|
I2C_CTL0(i2c_periph) = ctl;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief whether or not to response to a general Cal
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] gcallpara:
|
||
|
|
\arg I2C_GCEN_ENABLE: slave will response to a general call
|
||
|
|
\arg I2C_GCEN_DISABLE: slave will not response to a general call
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
|
||
|
|
{
|
||
|
|
/* configure slave response to a general call enable or disable */
|
||
|
|
uint32_t ctl = 0U;
|
||
|
|
ctl = I2C_CTL0(i2c_periph);
|
||
|
|
ctl &= ~(I2C_CTL0_GCEN);
|
||
|
|
ctl |= gcallpara;
|
||
|
|
I2C_CTL0(i2c_periph) = ctl;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief software reset I2C
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] sreset:
|
||
|
|
\arg I2C_SRESET_SET: I2C is under reset
|
||
|
|
\arg I2C_SRESET_RESET: I2C is not under reset
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
|
||
|
|
{
|
||
|
|
/* modify CTL0 and configure software reset I2C state */
|
||
|
|
uint32_t ctl = 0U;
|
||
|
|
ctl = I2C_CTL0(i2c_periph);
|
||
|
|
ctl &= ~(I2C_CTL0_SRESET);
|
||
|
|
ctl |= sreset;
|
||
|
|
I2C_CTL0(i2c_periph) = ctl;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief check i2c state
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] state:
|
||
|
|
\arg I2C_SBSEND: start condition send out
|
||
|
|
\arg I2C_ADDSEND: address is sent in master mode or received and matches in slave mode
|
||
|
|
\arg I2C_BTC: byte transmission finishes
|
||
|
|
\arg I2C_ADD10SEND: header of 10-bit address is sent in master mode
|
||
|
|
\arg I2C_STPDET: etop condition detected in slave mode
|
||
|
|
\arg I2C_RBNE: I2C_DATA is not Empty during receiving
|
||
|
|
\arg I2C_TBE: I2C_DATA is empty during transmitting
|
||
|
|
\arg I2C_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
|
||
|
|
\arg I2C_LOSTARB: arbitration lost in master mode
|
||
|
|
\arg I2C_AERR: acknowledge error
|
||
|
|
\arg I2C_OUERR: over-run or under-run situation occurs in slave mode
|
||
|
|
\arg I2C_PECERR: PEC error when receiving data
|
||
|
|
\arg I2C_SMBTO: timeout signal in SMBus mode
|
||
|
|
\arg I2C_SMBALT: SMBus alert status
|
||
|
|
\arg I2C_MASTER: a flag indicating whether I2C block is in master or slave mode
|
||
|
|
\arg I2C_I2CBSY: busy flag
|
||
|
|
\arg I2C_TRS: whether the I2C is a transmitter or a receiver
|
||
|
|
\arg I2C_RXGC: general call address (00h) received
|
||
|
|
\arg I2C_DEFSMB: default address of SMBus device
|
||
|
|
\arg I2C_HSTSMB: SMBus host header detected in slave mode
|
||
|
|
\arg I2C_DUMODF: dual flag in slave mode indicating which address is matched in dual-address mode
|
||
|
|
\param[out] none
|
||
|
|
\retval state of i2c
|
||
|
|
*/
|
||
|
|
FlagStatus i2c_flag_get(uint32_t i2c_periph,uint32_t state )
|
||
|
|
{
|
||
|
|
uint32_t reg = 0U;
|
||
|
|
FlagStatus regstate = RESET;
|
||
|
|
/* get the state in which register */
|
||
|
|
reg = (BIT(31) & state);
|
||
|
|
if((BIT(31) == reg)){
|
||
|
|
if((I2C_STAT1(i2c_periph)&(state & I2C_STATE_MASK))){
|
||
|
|
regstate = SET;
|
||
|
|
}else{
|
||
|
|
regstate = RESET;
|
||
|
|
}
|
||
|
|
}else{
|
||
|
|
if((I2C_STAT0(i2c_periph)&(state & I2C_STATE_MASK))){
|
||
|
|
regstate = SET;
|
||
|
|
}else{
|
||
|
|
regstate = RESET;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/* return the state */
|
||
|
|
return regstate;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief clear i2c state
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] state: state type
|
||
|
|
\@arg I2C_STAT0_SMBALT: SMBus Alert status
|
||
|
|
\@arg I2C_STAT0_SMBTO: timeout signal in SMBus mode
|
||
|
|
\@arg I2C_STAT0_PECERR: PEC error when receiving data
|
||
|
|
\@arg I2C_STAT0_OUERR: over-run or under-run situation occurs in slave mode
|
||
|
|
\@arg I2C_STAT0_AERR: acknowledge error
|
||
|
|
\@arg I2C_STAT0_LOSTARB: arbitration lost in master mode
|
||
|
|
\@arg I2C_STAT0_BERR: a bus error
|
||
|
|
\@arg I2C_STAT0_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_flag_clear(uint32_t i2c_periph,uint32_t state)
|
||
|
|
{
|
||
|
|
if(I2C_STAT0_ADDSEND == state){
|
||
|
|
/* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
|
||
|
|
I2C_STAT0(i2c_periph);
|
||
|
|
I2C_STAT1(i2c_periph);
|
||
|
|
}else{
|
||
|
|
I2C_STAT0(i2c_periph) &= ~(state);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief enable i2c interrupt
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] inttype: interrupt type
|
||
|
|
\arg I2C_CTL1_ERRIE: error interrupt enable
|
||
|
|
\arg I2C_CTL1_EVIE: event interrupt enable
|
||
|
|
\arg I2C_CTL1_BUFIE: buffer interrupt enable
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_interrupt_enable(uint32_t i2c_periph,uint32_t inttype)
|
||
|
|
{
|
||
|
|
I2C_CTL1(i2c_periph) |= (inttype);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief disable i2c interrupt
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] inttype: interrupt type
|
||
|
|
\arg I2C_CTL1_ERRIE: error interrupt enable
|
||
|
|
\arg I2C_CTL1_EVIE: event interrupt enable
|
||
|
|
\arg I2C_CTL1_BUFIE: buffer interrupt enable
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_interrupt_disable(uint32_t i2c_periph,uint32_t inttype)
|
||
|
|
{
|
||
|
|
I2C_CTL1(i2c_periph) &= ~(inttype);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief I2C PEC calculation on or off
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] pecpara:
|
||
|
|
\arg I2C_PEC_ENABLE: PEC calculation on
|
||
|
|
\arg I2C_PEC_DISABLE: PEC calculation off
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_pec_enable(uint32_t i2c_periph,uint32_t pecstate)
|
||
|
|
{
|
||
|
|
/* on/off PEC calculation */
|
||
|
|
uint32_t ctl = 0U;
|
||
|
|
ctl = I2C_CTL0(i2c_periph);
|
||
|
|
ctl &= ~(I2C_CTL0_PECEN);
|
||
|
|
ctl |= pecstate;
|
||
|
|
I2C_CTL0(i2c_periph) = ctl;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief I2C whether to transfer PEC value
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] pecpara:
|
||
|
|
\arg I2C_PECTRANS_ENABLE: transfer PEC
|
||
|
|
\arg I2C_PECTRANS_DISABLE: not transfer PEC
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_pec_transfer_enable(uint32_t i2c_periph,uint32_t pecpara)
|
||
|
|
{
|
||
|
|
/* whether to transfer PEC */
|
||
|
|
uint32_t ctl = 0U;
|
||
|
|
ctl = I2C_CTL0(i2c_periph);
|
||
|
|
ctl &= ~(I2C_CTL0_PECTRANS);
|
||
|
|
ctl |= pecpara;
|
||
|
|
I2C_CTL0(i2c_periph) = ctl;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief packet error checking value
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[out] none
|
||
|
|
\retval PEC value
|
||
|
|
*/
|
||
|
|
uint8_t i2c_pec_value(uint32_t i2c_periph)
|
||
|
|
{
|
||
|
|
return (uint8_t)((I2C_STAT1(i2c_periph) &I2C_STAT1_ECV)>>8);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief I2C issue alert through SMBA pin
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] smbuspara:
|
||
|
|
\arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin
|
||
|
|
\arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_smbus_alert_issue(uint32_t i2c_periph,uint32_t smbuspara)
|
||
|
|
{
|
||
|
|
/* issue alert through SMBA pin configure*/
|
||
|
|
uint32_t ctl = 0U;
|
||
|
|
ctl = I2C_CTL0(i2c_periph);
|
||
|
|
ctl &= ~(I2C_CTL0_SALT);
|
||
|
|
ctl |= smbuspara;
|
||
|
|
I2C_CTL0(i2c_periph) = ctl;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief I2C ARP protocol in SMBus switch enable or disable
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] smbuspara:
|
||
|
|
\arg I2C_ARP_ENABLE: ARP is enabled
|
||
|
|
\arg I2C_ARP_DISABLE: ARP is disabled
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_smbus_arp_enable(uint32_t i2c_periph,uint32_t arpstate)
|
||
|
|
{
|
||
|
|
/* enable or disable I2C ARP protocol*/
|
||
|
|
uint32_t ctl = 0U;
|
||
|
|
ctl = I2C_CTL0(i2c_periph);
|
||
|
|
ctl &= ~(I2C_CTL0_ARPEN);
|
||
|
|
ctl |= arpstate;
|
||
|
|
I2C_CTL0(i2c_periph) = ctl;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief analog noise filter disable
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_analog_noise_filter_disable(uint32_t i2c_periph)
|
||
|
|
{
|
||
|
|
I2C_FCTL(i2c_periph) |= I2C_FCTL_AFD;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief analog noise filter enable
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_analog_noise_filter_enable(uint32_t i2c_periph)
|
||
|
|
{
|
||
|
|
I2C_FCTL(i2c_periph) &= ~(I2C_FCTL_AFD);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief digital noise filter configuration
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] dfilterpara: refer to enum i2c_gcall_config_enum
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_digital_noise_filter_config(uint32_t i2c_periph,i2c_digital_filter_enum dfilterpara)
|
||
|
|
{
|
||
|
|
I2C_FCTL(i2c_periph) |= dfilterpara;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief enable SAM_V interface
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_sam_enable(uint32_t i2c_periph)
|
||
|
|
{
|
||
|
|
I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief disable SAM_V interface
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_sam_disable(uint32_t i2c_periph)
|
||
|
|
{
|
||
|
|
I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief enable SAM_V interface timeout detect
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_sam_timeout_enable(uint32_t i2c_periph)
|
||
|
|
{
|
||
|
|
I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief disable SAM_V interface timeout detect
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_sam_timeout_disable(uint32_t i2c_periph)
|
||
|
|
{
|
||
|
|
I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief enable the specified I2C SAM interrupt
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] inttype: interrupt type
|
||
|
|
\@arg I2C_SAMCS_TFFIE: txframe fall interrupt
|
||
|
|
\@arg I2C_SAMCS_TFRIE: txframe rise interrupt
|
||
|
|
\@arg I2C_SAMCS_RFFIE: rxframe fall interrupt
|
||
|
|
\@arg I2C_SAMCS_RFRIE: rxframe rise interrupt
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_sam_interrupt_enable(uint32_t i2c_periph,uint32_t inttype)
|
||
|
|
{
|
||
|
|
I2C_SAMCS(i2c_periph) |= (inttype);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief disable i2c interrupt
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] inttype: interrupt type
|
||
|
|
\@arg I2C_SAMCS_TFFIE: txframe fall interrupt
|
||
|
|
\@arg I2C_SAMCS_TFRIE: txframe rise interrupt
|
||
|
|
\@arg I2C_SAMCS_RFFIE: rxframe fall interrupt
|
||
|
|
\@arg I2C_SAMCS_RFRIE: rxframe rise interrupt
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_sam_interrupt_disable(uint32_t i2c_periph,uint32_t inttype)
|
||
|
|
{
|
||
|
|
I2C_SAMCS(i2c_periph) &= ~(inttype);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief check i2c SAM state
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] samstate: state type
|
||
|
|
\@arg I2C_SAMCS_TXF: level of txframe signal
|
||
|
|
\@arg I2C_SAMCS_RXF: level of rxframe signal
|
||
|
|
\@arg I2C_SAMCS_TFF: txframe fall flag
|
||
|
|
\@arg I2C_SAMCS_TFR: txframe rise flag
|
||
|
|
\@arg I2C_SAMCS_RFF: rxframe fall flag
|
||
|
|
\@arg I2C_SAMCS_RFR: rxframe rise flag
|
||
|
|
\param[out] none
|
||
|
|
\retval state of i2c SAM
|
||
|
|
*/
|
||
|
|
FlagStatus i2c_sam_flag_get(uint32_t i2c_periph,uint32_t samstate)
|
||
|
|
{
|
||
|
|
FlagStatus reg = RESET;
|
||
|
|
if(I2C_SAMCS(i2c_periph)&samstate){
|
||
|
|
reg =SET;
|
||
|
|
}else{
|
||
|
|
reg =RESET;
|
||
|
|
}
|
||
|
|
return reg;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief clear i2c SAM state
|
||
|
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||
|
|
\param[in] samstate: state type
|
||
|
|
\@arg I2C_SAMCS_TFF: txframe fall flag
|
||
|
|
\@arg I2C_SAMCS_TFR: txframe rise flag
|
||
|
|
\@arg I2C_SAMCS_RFF: rxframe fall flag
|
||
|
|
\@arg I2C_SAMCS_RFR: rxframe rise flag
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void i2c_sam_flag_clear(uint32_t i2c_periph,uint32_t samstate)
|
||
|
|
{
|
||
|
|
I2C_SAMCS(i2c_periph) &= ~(samstate);
|
||
|
|
|
||
|
|
}
|
||
|
|
|