349 lines
8.6 KiB
C
349 lines
8.6 KiB
C
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/*!
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\file gd32f4xx_pmu.c
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\brief PMU driver
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*/
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/*
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Copyright (C) 2016 GigaDevice
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2016-08-15, V1.0.0, firmware for GD32F4xx
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*/
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#include "gd32f4xx_pmu.h"
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#include "core_cm4.h"
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/*!
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\brief reset PMU register
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_deinit(void)
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{
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/* reset PMU */
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rcu_periph_reset_enable(RCU_PMURST);
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rcu_periph_reset_disable(RCU_PMURST);
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}
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/*!
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\brief select low voltage detector threshold
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\param[in] pmu_lvdt_n:
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\arg PMU_LVDT_0: voltage threshold is 2.2V
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\arg PMU_LVDT_1: voltage threshold is 2.3V
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\arg PMU_LVDT_2: voltage threshold is 2.4V
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\arg PMU_LVDT_3: voltage threshold is 2.5V
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\arg PMU_LVDT_4: voltage threshold is 2.6V
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\arg PMU_LVDT_5: voltage threshold is 2.7V
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\arg PMU_LVDT_6: voltage threshold is 2.8V
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\arg PMU_LVDT_7: voltage threshold is 2.9V
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\param[out] none
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\retval none
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*/
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void pmu_lvd_select(uint32_t pmu_lvdt_n)
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{
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/* disable LVD */
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PMU_CTL &= ~PMU_CTL_LVDEN;
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/* clear LVDT bits */
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PMU_CTL &= ~PMU_CTL_LVDT;
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/* set LVDT bits according to pmu_lvdt_n */
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PMU_CTL |= pmu_lvdt_n;
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/* enable LVD */
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PMU_CTL |= PMU_CTL_LVDEN;
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}
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/*!
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\brief LDO output voltage select
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this bit set by software when the main PLL closed, before closing PLL, change the system clock to IRC16M or HXTAL
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\param[in] ldo_output:
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\arg PMU_LDOVS_LOW: low-driver mode enable in deep-sleep mode
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\arg PMU_LDOVS_MID: low-driver mode disable in deep-sleep mode
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\arg PMU_LDOVS_HIGH: low-driver mode disable in deep-sleep mode
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\param[out] none
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\retval none
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*/
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void pmu_ldo_output_select(uint32_t ldo_output)
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{
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PMU_CTL &= ~PMU_CTL_LDOVS;
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PMU_CTL |= ldo_output;
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}
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/*!
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\brief low-driver mode enable in deep-sleep mode
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\param[in] lowdr_mode:
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\arg PMU_LOWDRIVER_ENABLE: low-driver mode enable in deep-sleep mode
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\arg PMU_LOWDRIVER_DISABLE: low-driver mode disable in deep-sleep mode
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\param[out] none
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\retval none
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*/
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void pmu_low_driver_mode_enable(uint32_t lowdr_mode)
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{
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PMU_CTL &= ~PMU_CTL_LDEN;
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PMU_CTL |= lowdr_mode;
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}
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/*!
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\brief high-driver mode switch
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this bit set by software only when IRC16M or HXTAL used as system clock
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\param[in] highdr_switch:
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\arg PMU_HIGHDR_SWITCH_NONE: no high-driver mode switch
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\arg PMU_HIGHDR_SWITCH_EN: high-driver mode switch
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\param[out] none
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\retval none
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*/
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void pmu_highdriver_switch_select(uint32_t highdr_switch)
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{
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/* wait for HDRF flag set */
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while(SET != pmu_flag_get(PMU_FLAG_HDRF)){
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}
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PMU_CTL &= ~PMU_CTL_HDS;
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PMU_CTL |= highdr_switch;
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}
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/*!
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\brief enable high-driver mode
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this bit set by software only when IRC16M or HXTAL used as system clock
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_highdriver_mode_enable(void)
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{
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PMU_CTL |= PMU_CTL_HDEN;
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}
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/*!
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\brief disable high-driver mode
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_highdriver_mode_disable(void)
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{
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PMU_CTL &= ~PMU_CTL_HDEN;
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}
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/*!
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\brief disable PMU lvd
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_lvd_disable(void)
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{
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/* disable LVD */
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PMU_CTL &= ~PMU_CTL_LVDEN;
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}
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/*!
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\brief low-driver mode when use low power LDO
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\param[in] mode:
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\arg PMU_NORMALDR_LOWPWR: normal driver when use low power LDO
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\arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO
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\param[out] none
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\retval none
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*/
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void pmu_lowdriver_lowpower_config(uint32_t mode)
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{
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PMU_CTL &= ~PMU_CTL_LDLP;
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PMU_CTL |= mode;
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}
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/*!
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\brief low-driver mode when use normal power LDO
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\param[in] mode:
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\arg PMU_NORMALDR_NORMALPWR: normal driver when use low power LDO
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\arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use low power LDO
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\param[out] none
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\retval none
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*/
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void pmu_lowdriver_normalpower_config(uint32_t mode)
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{
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PMU_CTL &= ~PMU_CTL_LDNP;
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PMU_CTL |= mode;
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}
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/*!
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\brief PMU work at sleep mode
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\param[in] sleepmodecmd:
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\arg WFI_CMD: use WFI command
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\arg WFE_CMD: use WFE command
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\param[out] none
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\retval none
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*/
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void pmu_to_sleepmode(uint8_t sleepmodecmd)
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{
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/* clear sleepdeep bit of Cortex-M4 system control register */
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SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
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/* select WFI or WFE command to enter sleep mode */
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if(WFI_CMD == sleepmodecmd){
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__WFI();
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}else{
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__WFE();
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}
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}
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/*!
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\brief PMU work at deepsleep mode
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\param[in] pmu_ldo
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\arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode
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\arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
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\param[in] deepsleepmodecmd:
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\arg WFI_CMD: use WFI command
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\arg WFE_CMD: use WFE command
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\param[out] none
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\retval none
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*/
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void pmu_to_deepsleepmode(uint32_t pmu_ldo,uint8_t deepsleepmodecmd)
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{
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/* clear stbmod and ldolp bits */
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PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
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/* set ldolp bit according to pmu_ldo */
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PMU_CTL |= pmu_ldo;
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/* set sleepdeep bit of Cortex-M4 system control register */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* select WFI or WFE command to enter deepsleep mode */
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if(WFI_CMD == deepsleepmodecmd){
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__WFI();
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}else{
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__SEV();
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__WFE();
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__WFE();
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}
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/* reset sleepdeep bit of Cortex-M4 system control register */
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SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
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}
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/*!
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\brief pmu work at standby mode
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\param[in] standbymodecmd:
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\arg WFI_CMD: use WFI command
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\arg WFE_CMD: use WFE command
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\param[out] none
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\retval none
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*/
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void pmu_to_standbymode(uint8_t standbymodecmd)
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{
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/* set sleepdeep bit of Cortex-M4 system control register */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* set stbmod bit */
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PMU_CTL |= PMU_CTL_STBMOD;
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/* reset wakeup flag */
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PMU_CTL |= PMU_CTL_WURST;
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/* select WFI or WFE command to enter standby mode */
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if(WFI_CMD == standbymodecmd){
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__WFI();
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}else{
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__WFE();
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}
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}
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/*!
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\brief backup SRAM LDO on
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\param[in] bkp_ldo:
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\arg PMU_BLDOON_OFF: backup SRAM LDO closed
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\arg PMU_BLDOON_ON: open the backup SRAM LDO
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\param[out] none
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\retval none
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*/
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void pmu_backup_ldo_config(uint32_t bkp_ldo)
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{
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PMU_CS &= ~PMU_CS_BLDOON;
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PMU_CS |= bkp_ldo;
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}
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/*!
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\brief reset flag bit
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\param[in] flag_reset:
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\arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag
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\arg PMU_FLAG_RESET_STANDBY: reset standby flag
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\param[out] none
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\retval none
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*/
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void pmu_flag_reset(uint32_t flag_reset)
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{
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switch(flag_reset){
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case PMU_FLAG_RESET_WAKEUP:
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/* reset wakeup flag */
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PMU_CTL |= PMU_CTL_WURST;
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break;
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case PMU_FLAG_RESET_STANDBY:
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/* reset standby flag */
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PMU_CTL |= PMU_CTL_STBRST;
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break;
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default :
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break;
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}
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}
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/*!
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\brief get flag status
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\param[in] pmu_flag:
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\arg PMU_FLAG_WAKEUP: wakeup flag status
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\arg PMU_FLAG_STANDBY: standby flag status
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\arg PMU_FLAG_LVD: lvd flag status
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\arg PMU_FLAG_BLDORF: backup SRAM LDO ready flag
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\arg PMU_FLAG_LDOVSRF: LDO voltage select ready flag
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\arg PMU_FLAG_HDRF: high-driver ready flag
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\arg PMU_FLAG_HDSRF: high-driver switch ready flag
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\arg PMU_FLAG_LDRF: low-driver mode ready flag
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\param[out] none
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\retval FlagStatus SET or RESET
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*/
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FlagStatus pmu_flag_get(uint32_t pmu_flag )
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{
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if(PMU_CS & pmu_flag){
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return SET;
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}
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return RESET;
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}
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/*!
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\brief enable backup domain write
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_backup_write_enable(void)
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{
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PMU_CTL |= PMU_CTL_BKPWEN;
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}
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/*!
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\brief disable backup domain write
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_backup_write_disable(void)
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{
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PMU_CTL &= ~PMU_CTL_BKPWEN;
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}
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/*!
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\brief enable wakeup pin
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_wakeup_pin_enable(void)
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{
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PMU_CS |= PMU_CS_WUPEN;
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}
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/*!
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\brief disable wakeup pin
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_wakeup_pin_disable(void)
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{
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PMU_CS &= ~PMU_CS_WUPEN;
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}
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