290 lines
10 KiB
C
290 lines
10 KiB
C
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/**
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******************************************************************************
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* @file system_stm32g0xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32g0xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to
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* configure the system clock before to branch to main program.
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*
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* This file configures the system clock as follows:
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*=============================================================================
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*-----------------------------------------------------------------------------
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* System Clock source | HSI
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 16000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 16000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB Prescaler | 1
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*-----------------------------------------------------------------------------
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* HSI Division factor | 1
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*-----------------------------------------------------------------------------
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* PLL_M | 1
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*-----------------------------------------------------------------------------
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* PLL_N | 8
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*-----------------------------------------------------------------------------
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* PLL_P | 7
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*-----------------------------------------------------------------------------
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* PLL_Q | 2
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*-----------------------------------------------------------------------------
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* PLL_R | 2
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*-----------------------------------------------------------------------------
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* Require 48MHz for RNG | Disabled
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*-----------------------------------------------------------------------------
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*=============================================================================
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32g0xx_system
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* @{
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*/
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/** @addtogroup STM32G0xx_System_Private_Includes
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* @{
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*/
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#include "stm32g0xx.h"
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#if !defined (HSE_VALUE)
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#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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#if !defined (LSI_VALUE)
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#define LSI_VALUE 32000U /*!< Value of LSI in Hz*/
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#endif /* LSI_VALUE */
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#if !defined (LSE_VALUE)
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#define LSE_VALUE 32768U /*!< Value of LSE in Hz*/
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#endif /* LSE_VALUE */
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/**
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* @}
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*/
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/** @addtogroup STM32G0xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32G0xx_System_Private_Defines
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* @{
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*/
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field.
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This value must be a multiple of 0x100. */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32G0xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32G0xx_System_Private_Variables
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* @{
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*/
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/* The SystemCoreClock variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 16000000U;
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const uint32_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
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const uint32_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
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/**
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* @}
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*/
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/** @addtogroup STM32G0xx_System_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32G0xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
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*
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* - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE
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*
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* - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
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* or HSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
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* 16 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
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* 8 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp;
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uint32_t pllvco;
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uint32_t pllr;
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uint32_t pllsource;
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uint32_t pllm;
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uint32_t hsidiv;
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (RCC->CFGR & RCC_CFGR_SWS)
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{
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case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
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SystemCoreClock = HSE_VALUE;
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break;
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case RCC_CFGR_SWS_LSI: /* LSI used as system clock */
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SystemCoreClock = LSI_VALUE;
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break;
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case RCC_CFGR_SWS_LSE: /* LSE used as system clock */
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SystemCoreClock = LSE_VALUE;
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break;
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case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
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{
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pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
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pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
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switch (pllsource)
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{
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case 0x03: /* HSE used as PLL clock source */
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pllvco = (HSE_VALUE / pllm);
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break;
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case 0x02: /* HSI used as PLL clock source */
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default:
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pllvco = (HSI_VALUE / pllm);
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break;
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}
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pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
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pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U);
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SystemCoreClock = pllvco/pllr;
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break;
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}
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case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
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default: /* HSI used as system clock */
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hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
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SystemCoreClock = (HSI_VALUE/hsidiv);
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break;
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}
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/* Compute HCLK clock frequency --------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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