557 lines
21 KiB
C
557 lines
21 KiB
C
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/*!
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*******************************************************************************
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**
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** \file gh_efuse.h
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**
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** \brief EFUSE controller.
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**
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** Copyright: 2012 - 2013 (C) GoKe Microelectronics ShangHai Branch
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**
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** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS
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** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
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** OMMISSIONS.
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**
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** \note Do not modify this file as it is generated automatically.
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**
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******************************************************************************/
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#ifndef _GH_EFUSE_H
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#define _GH_EFUSE_H
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#ifdef __LINUX__
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#include "reg4linux.h"
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#else
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#define FIO_ADDRESS(block,address) (address)
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#define FIO_MOFFSET(block,moffset) (moffset)
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#endif
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#ifndef __LINUX__
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#include "gtypes.h" /* global type definitions */
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#include "gh_lib_cfg.h" /* configuration */
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#endif
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#define GH_EFUSE_ENABLE_DEBUG_PRINT 0
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#ifdef __LINUX__
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#define GH_EFUSE_DEBUG_PRINT_FUNCTION printk
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#else
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#define GH_EFUSE_DEBUG_PRINT_FUNCTION printf
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#endif
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#ifndef __LINUX__
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#if GH_EFUSE_ENABLE_DEBUG_PRINT
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#include <stdio.h>
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#endif
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#endif
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/* check configuration */
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#ifndef GH_INLINE_LEVEL
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#error "GH_INLINE_LEVEL is not defined!"
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#endif
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#if GH_INLINE_LEVEL > 2
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#error "GH_INLINE_LEVEL must be set 0, 1 or 2!"
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#endif
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#ifndef GH_INLINE
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#error "GH_INLINE is not defined!"
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#endif
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/* disable inlining for debugging */
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#ifdef DEBUG
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#undef GH_INLINE_LEVEL
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#define GH_INLINE_LEVEL 0
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#endif
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/*----------------------------------------------------------------------------*/
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/* registers */
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/*----------------------------------------------------------------------------*/
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#define REG_EFUSE_KEY FIO_ADDRESS(EFUSE,0x90001000) /* read */
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#define REG_EFUSE_DATA FIO_ADDRESS(EFUSE,0x90001010) /* read */
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#define REG_EFUSE_USER_DATA FIO_ADDRESS(EFUSE,0x90001014) /* read */
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#define REG_EFUSE_CTRL FIO_ADDRESS(EFUSE,0x90001100) /* read/write */
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#define REG_EFUSE_BOOT FIO_ADDRESS(EFUSE,0x90001104) /* read/write */
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/*----------------------------------------------------------------------------*/
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/* bit group structures */
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/*----------------------------------------------------------------------------*/
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typedef union { /* EFUSE_Data */
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U32 all;
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struct {
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U32 boot_mode_sel : 1;
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U32 engine_sel : 1;
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U32 user_data : 30;
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} bitc;
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} GH_EFUSE_DATA_S;
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typedef union { /* EFUSE_CTRL */
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U32 all;
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struct {
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U32 wr_progen_high_cnt : 9;
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U32 wr_progen_low_cnt : 6;
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U32 wr_addr_setup_cnt : 4;
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U32 rd_addr_setup_cnt : 3;
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U32 rd_prchg_setup_cnt : 2;
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U32 rd_prchg_hold_cnt : 2;
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U32 rd_sense_hold_cnt : 3;
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U32 wait_rd_addr_update_cnt : 3;
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} bitc;
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} GH_EFUSE_CTRL_S;
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typedef union { /* EFUSE_BOOT */
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U32 all;
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struct {
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U32 en : 1;
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U32 rd_ok : 1;
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U32 : 30;
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} bitc;
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} GH_EFUSE_BOOT_S;
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/*----------------------------------------------------------------------------*/
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/* mirror variables */
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/*----------------------------------------------------------------------------*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*----------------------------------------------------------------------------*/
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/* register EFUSE_KEY (read) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL == 0
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/*! \brief Reads the register 'EFUSE_KEY'. */
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U32 GH_EFUSE_get_KEY(U8 index);
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#else /* GH_INLINE_LEVEL == 0 */
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GH_INLINE U32 GH_EFUSE_get_KEY(U8 index)
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{
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U32 value = (*(volatile U32 *)(REG_EFUSE_KEY + index * FIO_MOFFSET(EFUSE,0x00000004)));
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#if GH_EFUSE_ENABLE_DEBUG_PRINT
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GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_KEY] --> 0x%08x\n",
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(REG_EFUSE_KEY + index * FIO_MOFFSET(EFUSE,0x00000004)),value);
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#endif
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return value;
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}
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#endif /* GH_INLINE_LEVEL == 0 */
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/*----------------------------------------------------------------------------*/
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/* register EFUSE_Data (read) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL == 0
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/*! \brief Reads the register 'EFUSE_Data'. */
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U32 GH_EFUSE_get_Data(U8 index);
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/*! \brief Reads the bit group 'boot_mode_sel' of register 'EFUSE_Data'. */
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U8 GH_EFUSE_get_Data_boot_mode_sel(U8 index);
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/*! \brief Reads the bit group 'engine_sel' of register 'EFUSE_Data'. */
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U8 GH_EFUSE_get_Data_engine_sel(U8 index);
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/*! \brief Reads the bit group 'User_Data' of register 'EFUSE_Data'. */
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U32 GH_EFUSE_get_Data_User_Data(U8 index);
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#else /* GH_INLINE_LEVEL == 0 */
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GH_INLINE U32 GH_EFUSE_get_Data(U8 index)
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{
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U32 value = (*(volatile U32 *)(REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)));
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#if GH_EFUSE_ENABLE_DEBUG_PRINT
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GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_Data] --> 0x%08x\n",
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(REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)),value);
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#endif
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return value;
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}
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GH_INLINE U8 GH_EFUSE_get_Data_boot_mode_sel(U8 index)
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{
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GH_EFUSE_DATA_S tmp_value;
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U32 value = (*(volatile U32 *)(REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)));
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tmp_value.all = value;
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#if GH_EFUSE_ENABLE_DEBUG_PRINT
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GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_Data_boot_mode_sel] --> 0x%08x\n",
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(REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)),value);
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#endif
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return tmp_value.bitc.boot_mode_sel;
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}
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GH_INLINE U8 GH_EFUSE_get_Data_engine_sel(U8 index)
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{
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GH_EFUSE_DATA_S tmp_value;
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U32 value = (*(volatile U32 *)(REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)));
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tmp_value.all = value;
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#if GH_EFUSE_ENABLE_DEBUG_PRINT
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GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_Data_engine_sel] --> 0x%08x\n",
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(REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)),value);
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#endif
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return tmp_value.bitc.engine_sel;
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}
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GH_INLINE U32 GH_EFUSE_get_Data_User_Data(U8 index)
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{
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GH_EFUSE_DATA_S tmp_value;
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U32 value = (*(volatile U32 *)(REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)));
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tmp_value.all = value;
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#if GH_EFUSE_ENABLE_DEBUG_PRINT
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GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_Data_User_Data] --> 0x%08x\n",
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(REG_EFUSE_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)),value);
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#endif
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return tmp_value.bitc.user_data;
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}
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#endif /* GH_INLINE_LEVEL == 0 */
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/*----------------------------------------------------------------------------*/
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/* register EFUSE_User_Data (read) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL == 0
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/*! \brief Reads the register 'EFUSE_User_Data'. */
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U32 GH_EFUSE_get_User_Data(U8 index);
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#else /* GH_INLINE_LEVEL == 0 */
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GH_INLINE U32 GH_EFUSE_get_User_Data(U8 index)
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{
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U32 value = (*(volatile U32 *)(REG_EFUSE_USER_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)));
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#if GH_EFUSE_ENABLE_DEBUG_PRINT
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GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_User_Data] --> 0x%08x\n",
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(REG_EFUSE_USER_DATA + index * FIO_MOFFSET(EFUSE,0x00000004)),value);
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#endif
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return value;
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}
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#endif /* GH_INLINE_LEVEL == 0 */
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/*----------------------------------------------------------------------------*/
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/* register EFUSE_CTRL (read/write) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL == 0
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/*! \brief Writes the register 'EFUSE_CTRL'. */
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void GH_EFUSE_set_CTRL(U32 data);
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/*! \brief Reads the register 'EFUSE_CTRL'. */
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U32 GH_EFUSE_get_CTRL(void);
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/*! \brief Writes the bit group 'wr_progen_high_cnt' of register 'EFUSE_CTRL'. */
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void GH_EFUSE_set_CTRL_wr_progen_high_cnt(U16 data);
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/*! \brief Reads the bit group 'wr_progen_high_cnt' of register 'EFUSE_CTRL'. */
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U16 GH_EFUSE_get_CTRL_wr_progen_high_cnt(void);
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/*! \brief Writes the bit group 'wr_progen_low_cnt' of register 'EFUSE_CTRL'. */
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void GH_EFUSE_set_CTRL_wr_progen_low_cnt(U8 data);
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/*! \brief Reads the bit group 'wr_progen_low_cnt' of register 'EFUSE_CTRL'. */
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U8 GH_EFUSE_get_CTRL_wr_progen_low_cnt(void);
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/*! \brief Writes the bit group 'wr_addr_setup_cnt' of register 'EFUSE_CTRL'. */
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void GH_EFUSE_set_CTRL_wr_addr_setup_cnt(U8 data);
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/*! \brief Reads the bit group 'wr_addr_setup_cnt' of register 'EFUSE_CTRL'. */
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U8 GH_EFUSE_get_CTRL_wr_addr_setup_cnt(void);
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/*! \brief Writes the bit group 'rd_addr_setup_cnt' of register 'EFUSE_CTRL'. */
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void GH_EFUSE_set_CTRL_rd_addr_setup_cnt(U8 data);
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/*! \brief Reads the bit group 'rd_addr_setup_cnt' of register 'EFUSE_CTRL'. */
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U8 GH_EFUSE_get_CTRL_rd_addr_setup_cnt(void);
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/*! \brief Writes the bit group 'rd_prchg_setup_cnt' of register 'EFUSE_CTRL'. */
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void GH_EFUSE_set_CTRL_rd_prchg_setup_cnt(U8 data);
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/*! \brief Reads the bit group 'rd_prchg_setup_cnt' of register 'EFUSE_CTRL'. */
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U8 GH_EFUSE_get_CTRL_rd_prchg_setup_cnt(void);
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/*! \brief Writes the bit group 'rd_prchg_hold_cnt' of register 'EFUSE_CTRL'. */
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void GH_EFUSE_set_CTRL_rd_prchg_hold_cnt(U8 data);
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/*! \brief Reads the bit group 'rd_prchg_hold_cnt' of register 'EFUSE_CTRL'. */
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U8 GH_EFUSE_get_CTRL_rd_prchg_hold_cnt(void);
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/*! \brief Writes the bit group 'rd_sense_hold_cnt' of register 'EFUSE_CTRL'. */
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void GH_EFUSE_set_CTRL_rd_sense_hold_cnt(U8 data);
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/*! \brief Reads the bit group 'rd_sense_hold_cnt' of register 'EFUSE_CTRL'. */
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U8 GH_EFUSE_get_CTRL_rd_sense_hold_cnt(void);
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/*! \brief Writes the bit group 'Wait_rd_addr_update_cnt' of register 'EFUSE_CTRL'. */
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void GH_EFUSE_set_CTRL_Wait_rd_addr_update_cnt(U8 data);
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/*! \brief Reads the bit group 'Wait_rd_addr_update_cnt' of register 'EFUSE_CTRL'. */
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U8 GH_EFUSE_get_CTRL_Wait_rd_addr_update_cnt(void);
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#else /* GH_INLINE_LEVEL == 0 */
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GH_INLINE void GH_EFUSE_set_CTRL(U32 data)
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{
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*(volatile U32 *)REG_EFUSE_CTRL = data;
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#if GH_EFUSE_ENABLE_DEBUG_PRINT
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GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL] <-- 0x%08x\n",
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REG_EFUSE_CTRL,data,data);
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#endif
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}
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GH_INLINE U32 GH_EFUSE_get_CTRL(void)
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{
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U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
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#if GH_EFUSE_ENABLE_DEBUG_PRINT
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GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL] --> 0x%08x\n",
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REG_EFUSE_CTRL,value);
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#endif
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return value;
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}
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GH_INLINE void GH_EFUSE_set_CTRL_wr_progen_high_cnt(U16 data)
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{
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GH_EFUSE_CTRL_S d;
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d.all = *(volatile U32 *)REG_EFUSE_CTRL;
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d.bitc.wr_progen_high_cnt = data;
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*(volatile U32 *)REG_EFUSE_CTRL = d.all;
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#if GH_EFUSE_ENABLE_DEBUG_PRINT
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GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_wr_progen_high_cnt] <-- 0x%08x\n",
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REG_EFUSE_CTRL,d.all,d.all);
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#endif
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}
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GH_INLINE U16 GH_EFUSE_get_CTRL_wr_progen_high_cnt(void)
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{
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GH_EFUSE_CTRL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
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tmp_value.all = value;
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#if GH_EFUSE_ENABLE_DEBUG_PRINT
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GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_wr_progen_high_cnt] --> 0x%08x\n",
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REG_EFUSE_CTRL,value);
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#endif
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return tmp_value.bitc.wr_progen_high_cnt;
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}
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GH_INLINE void GH_EFUSE_set_CTRL_wr_progen_low_cnt(U8 data)
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{
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GH_EFUSE_CTRL_S d;
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d.all = *(volatile U32 *)REG_EFUSE_CTRL;
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d.bitc.wr_progen_low_cnt = data;
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*(volatile U32 *)REG_EFUSE_CTRL = d.all;
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#if GH_EFUSE_ENABLE_DEBUG_PRINT
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GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_wr_progen_low_cnt] <-- 0x%08x\n",
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REG_EFUSE_CTRL,d.all,d.all);
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#endif
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}
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GH_INLINE U8 GH_EFUSE_get_CTRL_wr_progen_low_cnt(void)
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{
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GH_EFUSE_CTRL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
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tmp_value.all = value;
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#if GH_EFUSE_ENABLE_DEBUG_PRINT
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GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_wr_progen_low_cnt] --> 0x%08x\n",
|
||
|
|
REG_EFUSE_CTRL,value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.wr_progen_low_cnt;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_EFUSE_set_CTRL_wr_addr_setup_cnt(U8 data)
|
||
|
|
{
|
||
|
|
GH_EFUSE_CTRL_S d;
|
||
|
|
d.all = *(volatile U32 *)REG_EFUSE_CTRL;
|
||
|
|
d.bitc.wr_addr_setup_cnt = data;
|
||
|
|
*(volatile U32 *)REG_EFUSE_CTRL = d.all;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_wr_addr_setup_cnt] <-- 0x%08x\n",
|
||
|
|
REG_EFUSE_CTRL,d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_EFUSE_get_CTRL_wr_addr_setup_cnt(void)
|
||
|
|
{
|
||
|
|
GH_EFUSE_CTRL_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_wr_addr_setup_cnt] --> 0x%08x\n",
|
||
|
|
REG_EFUSE_CTRL,value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.wr_addr_setup_cnt;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_EFUSE_set_CTRL_rd_addr_setup_cnt(U8 data)
|
||
|
|
{
|
||
|
|
GH_EFUSE_CTRL_S d;
|
||
|
|
d.all = *(volatile U32 *)REG_EFUSE_CTRL;
|
||
|
|
d.bitc.rd_addr_setup_cnt = data;
|
||
|
|
*(volatile U32 *)REG_EFUSE_CTRL = d.all;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_rd_addr_setup_cnt] <-- 0x%08x\n",
|
||
|
|
REG_EFUSE_CTRL,d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_EFUSE_get_CTRL_rd_addr_setup_cnt(void)
|
||
|
|
{
|
||
|
|
GH_EFUSE_CTRL_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_rd_addr_setup_cnt] --> 0x%08x\n",
|
||
|
|
REG_EFUSE_CTRL,value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.rd_addr_setup_cnt;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_EFUSE_set_CTRL_rd_prchg_setup_cnt(U8 data)
|
||
|
|
{
|
||
|
|
GH_EFUSE_CTRL_S d;
|
||
|
|
d.all = *(volatile U32 *)REG_EFUSE_CTRL;
|
||
|
|
d.bitc.rd_prchg_setup_cnt = data;
|
||
|
|
*(volatile U32 *)REG_EFUSE_CTRL = d.all;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_rd_prchg_setup_cnt] <-- 0x%08x\n",
|
||
|
|
REG_EFUSE_CTRL,d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_EFUSE_get_CTRL_rd_prchg_setup_cnt(void)
|
||
|
|
{
|
||
|
|
GH_EFUSE_CTRL_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_rd_prchg_setup_cnt] --> 0x%08x\n",
|
||
|
|
REG_EFUSE_CTRL,value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.rd_prchg_setup_cnt;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_EFUSE_set_CTRL_rd_prchg_hold_cnt(U8 data)
|
||
|
|
{
|
||
|
|
GH_EFUSE_CTRL_S d;
|
||
|
|
d.all = *(volatile U32 *)REG_EFUSE_CTRL;
|
||
|
|
d.bitc.rd_prchg_hold_cnt = data;
|
||
|
|
*(volatile U32 *)REG_EFUSE_CTRL = d.all;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_rd_prchg_hold_cnt] <-- 0x%08x\n",
|
||
|
|
REG_EFUSE_CTRL,d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_EFUSE_get_CTRL_rd_prchg_hold_cnt(void)
|
||
|
|
{
|
||
|
|
GH_EFUSE_CTRL_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_rd_prchg_hold_cnt] --> 0x%08x\n",
|
||
|
|
REG_EFUSE_CTRL,value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.rd_prchg_hold_cnt;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_EFUSE_set_CTRL_rd_sense_hold_cnt(U8 data)
|
||
|
|
{
|
||
|
|
GH_EFUSE_CTRL_S d;
|
||
|
|
d.all = *(volatile U32 *)REG_EFUSE_CTRL;
|
||
|
|
d.bitc.rd_sense_hold_cnt = data;
|
||
|
|
*(volatile U32 *)REG_EFUSE_CTRL = d.all;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_rd_sense_hold_cnt] <-- 0x%08x\n",
|
||
|
|
REG_EFUSE_CTRL,d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_EFUSE_get_CTRL_rd_sense_hold_cnt(void)
|
||
|
|
{
|
||
|
|
GH_EFUSE_CTRL_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_rd_sense_hold_cnt] --> 0x%08x\n",
|
||
|
|
REG_EFUSE_CTRL,value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.rd_sense_hold_cnt;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_EFUSE_set_CTRL_Wait_rd_addr_update_cnt(U8 data)
|
||
|
|
{
|
||
|
|
GH_EFUSE_CTRL_S d;
|
||
|
|
d.all = *(volatile U32 *)REG_EFUSE_CTRL;
|
||
|
|
d.bitc.wait_rd_addr_update_cnt = data;
|
||
|
|
*(volatile U32 *)REG_EFUSE_CTRL = d.all;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_CTRL_Wait_rd_addr_update_cnt] <-- 0x%08x\n",
|
||
|
|
REG_EFUSE_CTRL,d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_EFUSE_get_CTRL_Wait_rd_addr_update_cnt(void)
|
||
|
|
{
|
||
|
|
GH_EFUSE_CTRL_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)REG_EFUSE_CTRL);
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_CTRL_Wait_rd_addr_update_cnt] --> 0x%08x\n",
|
||
|
|
REG_EFUSE_CTRL,value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.wait_rd_addr_update_cnt;
|
||
|
|
}
|
||
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
||
|
|
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
/* register EFUSE_BOOT (read/write) */
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
#if GH_INLINE_LEVEL == 0
|
||
|
|
/*! \brief Writes the register 'EFUSE_BOOT'. */
|
||
|
|
void GH_EFUSE_set_BOOT(U32 data);
|
||
|
|
/*! \brief Reads the register 'EFUSE_BOOT'. */
|
||
|
|
U32 GH_EFUSE_get_BOOT(void);
|
||
|
|
/*! \brief Writes the bit group 'EN' of register 'EFUSE_BOOT'. */
|
||
|
|
void GH_EFUSE_set_BOOT_EN(U8 data);
|
||
|
|
/*! \brief Reads the bit group 'EN' of register 'EFUSE_BOOT'. */
|
||
|
|
U8 GH_EFUSE_get_BOOT_EN(void);
|
||
|
|
/*! \brief Writes the bit group 'RD_OK' of register 'EFUSE_BOOT'. */
|
||
|
|
void GH_EFUSE_set_BOOT_RD_OK(U8 data);
|
||
|
|
/*! \brief Reads the bit group 'RD_OK' of register 'EFUSE_BOOT'. */
|
||
|
|
U8 GH_EFUSE_get_BOOT_RD_OK(void);
|
||
|
|
#else /* GH_INLINE_LEVEL == 0 */
|
||
|
|
GH_INLINE void GH_EFUSE_set_BOOT(U32 data)
|
||
|
|
{
|
||
|
|
*(volatile U32 *)REG_EFUSE_BOOT = data;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_BOOT] <-- 0x%08x\n",
|
||
|
|
REG_EFUSE_BOOT,data,data);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U32 GH_EFUSE_get_BOOT(void)
|
||
|
|
{
|
||
|
|
U32 value = (*(volatile U32 *)REG_EFUSE_BOOT);
|
||
|
|
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_BOOT] --> 0x%08x\n",
|
||
|
|
REG_EFUSE_BOOT,value);
|
||
|
|
#endif
|
||
|
|
return value;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_EFUSE_set_BOOT_EN(U8 data)
|
||
|
|
{
|
||
|
|
GH_EFUSE_BOOT_S d;
|
||
|
|
d.all = *(volatile U32 *)REG_EFUSE_BOOT;
|
||
|
|
d.bitc.en = data;
|
||
|
|
*(volatile U32 *)REG_EFUSE_BOOT = d.all;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_BOOT_EN] <-- 0x%08x\n",
|
||
|
|
REG_EFUSE_BOOT,d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_EFUSE_get_BOOT_EN(void)
|
||
|
|
{
|
||
|
|
GH_EFUSE_BOOT_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)REG_EFUSE_BOOT);
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_BOOT_EN] --> 0x%08x\n",
|
||
|
|
REG_EFUSE_BOOT,value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.en;
|
||
|
|
}
|
||
|
|
GH_INLINE void GH_EFUSE_set_BOOT_RD_OK(U8 data)
|
||
|
|
{
|
||
|
|
GH_EFUSE_BOOT_S d;
|
||
|
|
d.all = *(volatile U32 *)REG_EFUSE_BOOT;
|
||
|
|
d.bitc.rd_ok = data;
|
||
|
|
*(volatile U32 *)REG_EFUSE_BOOT = d.all;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_EFUSE_set_BOOT_RD_OK] <-- 0x%08x\n",
|
||
|
|
REG_EFUSE_BOOT,d.all,d.all);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
GH_INLINE U8 GH_EFUSE_get_BOOT_RD_OK(void)
|
||
|
|
{
|
||
|
|
GH_EFUSE_BOOT_S tmp_value;
|
||
|
|
U32 value = (*(volatile U32 *)REG_EFUSE_BOOT);
|
||
|
|
|
||
|
|
tmp_value.all = value;
|
||
|
|
#if GH_EFUSE_ENABLE_DEBUG_PRINT
|
||
|
|
GH_EFUSE_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_EFUSE_get_BOOT_RD_OK] --> 0x%08x\n",
|
||
|
|
REG_EFUSE_BOOT,value);
|
||
|
|
#endif
|
||
|
|
return tmp_value.bitc.rd_ok;
|
||
|
|
}
|
||
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
||
|
|
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
/* init function */
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
/*! \brief Initialises the registers and mirror variables. */
|
||
|
|
void GH_EFUSE_init(void);
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* _GH_EFUSE_H */
|
||
|
|
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
/* end of file */
|
||
|
|
/*----------------------------------------------------------------------------*/
|
||
|
|
|