219 lines
5.1 KiB
NASM
219 lines
5.1 KiB
NASM
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#include "macdefs.inc"
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name OS_Core
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COMMON INTVEC:CODE
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;********************************************************************
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;
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; function:
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; description: Trap 0x10 vector used for context switch
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; Right now, all TRAPs to $1x are trated the same way
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;
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org 50h
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jr OSCtxSW
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;********************************************************************
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;
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; function:
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; description: Timer 40 compare match interrupt used for system
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; tick interrupt
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;
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org 0x220
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jr OSTickIntr
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org 0x0520
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jr uarta1_int_r
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RSEG CODE(1)
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EXTERN rt_thread_switch_interrput_flag
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EXTERN rt_interrupt_from_thread
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EXTERN rt_interrupt_to_thread
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EXTERN rt_interrupt_enter
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EXTERN rt_interrupt_leave
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EXTERN rt_tick_increase
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EXTERN uarta1_receive_handler
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PUBLIC rt_hw_interrupt_disable
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PUBLIC rt_hw_interrupt_enable
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PUBLIC rt_hw_context_switch_to
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PUBLIC rt_hw_context_switch
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PUBLIC rt_hw_context_switch_interrupt
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PUBLIC OSCtxSW
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PUBLIC OS_Restore_CPU_Context
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rt_hw_interrupt_disable:
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stsr psw, r1
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di
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jmp [lp]
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rt_hw_interrupt_enable:
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ldsr r1, psw
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jmp [lp]
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OS_Restore_CPU_Context:
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mov sp, ep
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sld.w 4[ep], r2
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sld.w 8[ep], r5
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sld.w 12[ep],r6
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sld.w 16[ep],r7
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sld.w 20[ep],r8
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sld.w 24[ep],r9
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sld.w 28[ep],r10
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sld.w 32[ep],r11
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sld.w 36[ep],r12
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sld.w 40[ep],r13
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sld.w 44[ep],r14
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sld.w 48[ep],r15
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sld.w 52[ep],r16
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;See what was the latest interruption (trap or interrupt)
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stsr ecr, r17 ;Move ecr to r17
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mov 0x050,r1
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cmp r1, r17 ;If latest break was due to TRAP, set EP
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be _SetEP
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_ClrEP:
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mov 0x20, r17 ;Set only ID
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ldsr r17, psw
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;Restore caller address
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sld.w 56[ep], r1
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ldsr r1, EIPC
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;Restore PSW
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sld.w 60[ep], r1
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andi 0xffdf,r1,r1
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ldsr r1, EIPSW
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sld.w 0[ep], r1
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dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31}
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;Return from interrupt starts new task!
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reti
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_SetEP:
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mov 0x60, r17 ;Set both EIPC and ID bits
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ldsr r17, psw
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;Restore caller address
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sld.w 56[ep], r1
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ldsr r1, EIPC
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;Restore PSW
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sld.w 60[ep], r1
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andi 0xffdf,r1,r1
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ldsr r1, EIPSW
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sld.w 0[ep], r1
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dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31}
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;Return from interrupt starts new task!
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reti
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//rseg CODE:CODE
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//public rt_hw_context_switch_to
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rt_hw_context_switch_to:
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;Load stack pointer of the task to run
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ld.w 0[r1], sp ;load sp from struct
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;Restore all Processor registers from stack and return from interrupt
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jr OS_Restore_CPU_Context
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OSCtxSW:
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SAVE_CPU_CTX ;Save all CPU registers
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mov rt_thread_switch_interrput_flag, r1
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ld.w 0[r1],r5
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cmp 0, r5
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be exit
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mov 0, r5
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st.b r5, 0[r1]
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mov rt_interrupt_from_thread, r21
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ld.w 0[r21], r21
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st.w sp, 0[r21]
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mov rt_interrupt_to_thread, r1
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ld.w 0[r1], r1
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ld.w 0[r1], sp
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exit:
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;Restore all Processor registers from stack and return from interrupt
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jr OS_Restore_CPU_Context
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;R1 -> rt_interrupt_from_thread
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;R5 -> rt_interrupt_to_thread
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rt_hw_context_switch:
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mov rt_thread_switch_interrput_flag, r8
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ld.w 0[r8],r9
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cmp 1, r9
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be jump1
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;mov rt_thread_switch_interrput_flag, r1
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mov 1, r9
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st.b r9, 0[r8]
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mov rt_interrupt_from_thread, r10
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st.w r1, 0[r10]
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jump1
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mov rt_interrupt_to_thread, r11
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st.w r5, 0[r11]
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trap 0x10
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jmp [lp]
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rt_hw_context_switch_interrupt:
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mov rt_thread_switch_interrput_flag, r8
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ld.w 0[r8],r9
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cmp 1, r9
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be jump2
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;mov rt_thread_switch_interrput_flag, r1
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mov 1, r9
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st.b r9, 0[r8]
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mov rt_interrupt_from_thread, r10
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st.w r1, 0[r10]
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jump2
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mov rt_interrupt_to_thread, r11
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st.w r5, 0[r11]
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jmp [lp]
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rt_hw_context_switch_interrupt_do
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mov rt_thread_switch_interrput_flag, r8
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mov 0, r9
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st.b r9, 0[r8]
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mov rt_interrupt_from_thread, r21
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ld.w 0[r21], r21
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st.w sp, 0[r21]
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mov rt_interrupt_to_thread, r1
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ld.w 0[r1], r1
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ld.w 0[r1], sp
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jr OS_Restore_CPU_Context
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OSTickIntr:
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SAVE_CPU_CTX ;Save current task's registers
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jarl rt_interrupt_enter,lp
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jarl rt_tick_increase,lp
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jarl rt_interrupt_leave,lp
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mov rt_thread_switch_interrput_flag, r8
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ld.w 0[r8],r9
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cmp 1, r9
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be rt_hw_context_switch_interrupt_do
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jr OS_Restore_CPU_Context
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uarta1_int_r:
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SAVE_CPU_CTX ;Save current task's registers
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jarl rt_interrupt_enter,lp
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jarl uarta1_receive_handler,lp
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jarl rt_interrupt_leave,lp
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mov rt_thread_switch_interrput_flag, r8
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ld.w 0[r8],r9
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cmp 1, r9
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be rt_hw_context_switch_interrupt_do
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jr OS_Restore_CPU_Context
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END
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