70 lines
2.0 KiB
C
70 lines
2.0 KiB
C
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-06 SummerGift change to new framework
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*/
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#include "board.h"
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void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 1;
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RCC_OscInitStruct.PLL.PLLN = 20;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
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{
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Error_Handler();
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}
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
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PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
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{
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Error_Handler();
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}
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/**Configure the main internal regulator output voltage
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*/
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if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
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{
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Error_Handler();
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}
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}
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void MX_GPIO_Init(void)
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{
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/* GPIO Ports Clock Enable */
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__HAL_RCC_GPIOH_CLK_ENABLE();
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__HAL_RCC_GPIOA_CLK_ENABLE();
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}
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