196 lines
8.3 KiB
ArmAsm
196 lines
8.3 KiB
ArmAsm
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/**
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******************************************************************************
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* @file startup_stm32f10x_hd.s
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* @author MCD Application Team
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* @version V3.1.2
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* @date 09/28/2009
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* @brief STM32F10x High Density Devices vector table for RIDE7 toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address,
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* - Configure external SRAM mounted on STM3210E-EVAL board
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* to be used as data memory (optional, to be enabled by user)
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M3 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @copy
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
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*/
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.section .bss.init
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.equ Stack_Size, 0x00000200
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.space Stack_Size
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Initial_spTop:
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.syntax unified
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.cpu cortex-m3
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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// .equ Initial_spTop, 0x20000200
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.equ BootRAM, 0xF1E0F85F
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* restore original stack pointer */
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LDR r0, =Initial_spTop
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MSR msp, r0
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Call the application's entry point.*/
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bl main
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bx lr
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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*
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* @param None
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* @retval : None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M3. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word Initial_spTop
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.word Reset_Handler
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.word Default_Handler //NMI_Handler
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.word rt_hw_hard_fault
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.word Default_Handler //MemManage_Handler
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.word Default_Handler //BusFault_Handler
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.word Default_Handler //UsageFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word Default_Handler //SVC_Handler
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.word Default_Handler //DebugMon_Handler
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.word 0
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.word rt_hw_pend_sv
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.word rt_hw_timer_handler
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.word Default_Handler // GPIO Port A
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.word Default_Handler // GPIO Port B
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.word Default_Handler // GPIO Port C
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.word Default_Handler // GPIO Port D
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.word Default_Handler // GPIO Port E
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.word rt_hw_uart_isr_1 // UART0 Rx and Tx
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.word Default_Handler // UART1 Rx and Tx
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.word Default_Handler // SSI Rx and Tx
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.word Default_Handler // I2C Master and Slave
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.word Default_Handler // PWM Fault
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.word Default_Handler // PWM Generator 0
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.word Default_Handler // PWM Generator 1
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.word Default_Handler // PWM Generator 2
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.word Default_Handler // Quadrature Encoder
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.word Default_Handler // ADC Sequence 0
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.word Default_Handler // ADC Sequence 1
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.word Default_Handler // ADC Sequence 2
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.word Default_Handler // ADC Sequence 3
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.word Default_Handler // Watchdog timer
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.word Default_Handler // Timer 0 subtimer A
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.word Default_Handler // Timer 0 subtimer B
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.word Default_Handler // Timer 1 subtimer A
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.word Default_Handler // Timer 1 subtimer B
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.word Default_Handler // Timer 2 subtimer A
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.word Default_Handler // Timer 2 subtimer B
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.word Default_Handler // Analog Comparator 0
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.word Default_Handler // Analog Comparator 1
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.word Default_Handler // Analog Comparator 2
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.word Default_Handler // System Control (PLL, OSC,
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.word Default_Handler // FLASH Control
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.word Default_Handler // GPIO Port F
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.word Default_Handler // GPIO Port G
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.word Default_Handler // GPIO Port H
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.word Default_Handler // UART2 Rx and Tx
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.word Default_Handler // SSI1 Rx and Tx
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.word Default_Handler // Timer 3 subtimer A
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.word Default_Handler // Timer 3 subtimer B
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.word Default_Handler // I2C1 Master and Slave
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.word Default_Handler // Quadrature Encoder 1
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.word Default_Handler // CAN0
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.word Default_Handler // CAN1
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.word Default_Handler // CAN2
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.word luminaryif_isr // Ethernet
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.word Default_Handler // Hibernate
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.word Default_Handler // USB0
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.word Default_Handler // PWM Generator 3
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.word Default_Handler // uDMA Software Transfer
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.word Default_Handler // uDMA Error
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