449 lines
9.6 KiB
C
449 lines
9.6 KiB
C
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-07-15 Magicoe The first version for LPC55S6x
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*/
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#include "drv_spi.h"
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#include "fsl_common.h"
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#include "fsl_iocon.h"
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#include "fsl_spi.h"
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#if defined(BSP_USING_SPIBUS0) || \
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defined(BSP_USING_SPIBUS1) || \
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defined(BSP_USING_SPIBUS2) || \
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defined(BSP_USING_SPIBUS3) || \
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defined(BSP_USING_SPIBUS4) || \
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defined(BSP_USING_SPIBUS5) || \
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defined(BSP_USING_SPIBUS6) || \
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defined(BSP_USING_SPIBUS7) || \
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defined(BSP_USING_SPIBUS8)
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#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
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#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
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#endif
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struct lpc_spi
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{iteopuywqt[riouqwyyyyyyyyyyyy
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SPI_Type *base;
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struct rt_spi_configuration *cfg;
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SYSCON_RSTn_t spi_rst;
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};
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struct lpc_sw_spi_cs
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{
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rt_uint32_t pin;
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};
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static uint32_t lpc_get_spi_freq(SPI_Type *base)
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{
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uint32_t freq = 0;
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#if defined(BSP_USING_SPIBUS0)
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if(base == SPI0)
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{
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freq = CLOCK_GetFreq(kCLOCK_Flexcomm0);
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}
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#endif
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#if defined(BSP_USING_SPIBUS1)
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if(base == SPI1)
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{
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freq = CLOCK_GetFreq(kCLOCK_Flexcomm1);
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}
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#endif
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#if defined(BSP_USING_SPIBUS2)
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if(base == SPI2)
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{
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freq = CLOCK_GetFreq(kCLOCK_Flexcomm2);
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}
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#endif
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#if defined(BSP_USING_SPIBUS3)
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if(base == SPI3)
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{
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freq = CLOCK_GetFreq(kCLOCK_Flexcomm3);
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}
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#endif
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#if defined(BSP_USING_SPIBUS4)
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if(base == SPI4)
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{
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freq = CLOCK_GetFreq(kCLOCK_Flexcomm4);
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}
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#endif
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#if defined(BSP_USING_SPIBUS5)
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if(base == SPI5)
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{
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freq = CLOCK_GetFreq(kCLOCK_Flexcomm5);
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}
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#endif
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#if defined(BSP_USING_SPIBUS6)
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if(base == SPI6)
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{
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freq = CLOCK_GetFreq(kCLOCK_Flexcomm6);
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}
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#endif
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#if defined(BSP_USING_SPIBUS7)
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if(base == SPI7)
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{
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freq = CLOCK_GetFreq(kCLOCK_Flexcomm7);
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}
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#endif
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/* High Speed SPI - 50MHz */
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#if defined(BSP_USING_SPIBUS8)
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if(base == SPI8)
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{
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freq = CLOCK_GetFreq(kCLOCK_HsLspi);
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}
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#endif
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return freq;
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}
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static rt_err_t lpc_spi_init(SPI_Type *base, struct rt_spi_configuration *cfg)
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{
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spi_master_config_t masterConfig = {0};
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RT_ASSERT(cfg != RT_NULL);
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if(cfg->data_width != 8 && cfg->data_width != 16)
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{
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return (-RT_EINVAL);
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}
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SPI_MasterGetDefaultConfig(&masterConfig);
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#if defined(BSP_USING_SPIBUS8)
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if(base == SPI8)
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{
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if(cfg->max_hz > 50*1000*1000)
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{
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cfg->max_hz = 50*1000*1000;
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}
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}
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#else
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if(cfg->max_hz > 12*1000*1000)
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{
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cfg->max_hz = 12*1000*1000;
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}
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#endif
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masterConfig.baudRate_Bps = cfg->max_hz;
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if(cfg->data_width == 8)
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{
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masterConfig.dataWidth = kSPI_Data8Bits;
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}
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else if(cfg->data_width == 16)
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{
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masterConfig.dataWidth = kSPI_Data16Bits;
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}
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if(cfg->mode & RT_SPI_MSB)
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{
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masterConfig.direction = kSPI_MsbFirst;
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}
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else
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{
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masterConfig.direction = kSPI_LsbFirst;
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}
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if(cfg->mode & RT_SPI_CPHA)
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{
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masterConfig.phase = kSPI_ClockPhaseSecondEdge;
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}
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else
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{
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masterConfig.phase = kSPI_ClockPhaseFirstEdge;
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}
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if(cfg->mode & RT_SPI_CPOL)
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{
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masterConfig.polarity = kSPI_ClockPolarityActiveLow;
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}
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else
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{
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masterConfig.polarity = kSPI_ClockPolarityActiveHigh;
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}
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SPI_MasterInit(base, &masterConfig, lpc_get_spi_freq(base));
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return RT_EOK;
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}
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rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin)
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{
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rt_err_t ret = RT_EOK;
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struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
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RT_ASSERT(spi_device != RT_NULL);
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struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs));
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RT_ASSERT(cs_pin != RT_NULL);
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cs_pin->pin = pin;
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rt_pin_mode(pin, PIN_MODE_OUTPUT);
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rt_pin_write(pin, PIN_HIGH);
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ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
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return ret;
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}
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static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
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{
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rt_err_t ret = RT_EOK;
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struct lpc_spi *spi = RT_NULL;
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RT_ASSERT(cfg != RT_NULL);
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RT_ASSERT(device != RT_NULL);
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spi = (struct lpc_spi *)(device->bus->parent.user_data);
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spi->cfg = cfg;
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ret = lpc_spi_init(spi->base, cfg);
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return ret;
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}
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#define SPISTEP(datalen) (((datalen) == 8) ? 1 : 2)
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static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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uint32_t length;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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RT_ASSERT(device->bus->parent.user_data != RT_NULL);
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struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data);
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struct lpc_sw_spi_cs *cs = device->parent.user_data;
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if(message->cs_take)
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{
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rt_pin_write(cs->pin, PIN_LOW);
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}
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length = message->length;
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const rt_uint8_t *txData = (uint8_t *)(message->send_buf);
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rt_uint8_t *rxData = (uint8_t *)(message->recv_buf);
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rt_kprintf("*** spi send %d\r\n", length);
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while (length)
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{
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/* clear tx/rx errors and empty FIFOs */
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spi->base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
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spi->base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK;
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spi->base->FIFOWR = *txData | 0x07300000;
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/* wait if TX FIFO of previous transfer is not empty */
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while ((spi->base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) == 0) {
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}
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if(rxData != NULL)
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{
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*rxData = spi->base->FIFORD;
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rxData += SPISTEP(spi->cfg->data_width);
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}
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txData += SPISTEP(spi->cfg->data_width);;
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length--;
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}
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if(message->cs_release)
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{
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rt_pin_write(cs->pin, PIN_HIGH);
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}
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return (message->length - length);
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}
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#if defined(BSP_USING_SPIBUS0)
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static struct lpc_spi spi0 =
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{
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.base = SPI0
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};
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static struct rt_spi_bus spi0_bus =
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{
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.parent.user_data = &spi0
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};
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#endif
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#if defined(BSP_USING_SPIBUS1)
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static struct lpc_spi spi1 =
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{
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.base = SPI1
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};
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static struct rt_spi_bus spi1_bus =
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{
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.parent.user_data = &spi1
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};
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#endif
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#if defined(BSP_USING_SPIBUS2)
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static struct lpc_spi spi2 =
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{
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.base = SPI2
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};
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static struct rt_spi_bus spi2_bus =
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{
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.parent.user_data = &spi2
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};
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#endif
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#if defined(BSP_USING_SPIBUS3)
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static struct lpc_spi spi3 =
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{
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.base = SPI3
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};
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static struct rt_spi_bus spi3_bus =
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{
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.parent.user_data = &spi3
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};
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#endif
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#if defined(BSP_USING_SPIBUS4)
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static struct lpc_spi spi4 =
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{
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.base = SPI4
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};
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static struct rt_spi_bus spi4_bus =
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{
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.parent.user_data = &spi4
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};
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#endif
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#if defined(BSP_USING_SPIBUS5)
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static struct lpc_spi spi5 =
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{
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.base = SPI5
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};
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static struct rt_spi_bus spi5_bus =
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{
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.parent.user_data = &spi5
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};
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#endif
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#if defined(BSP_USING_SPIBUS6)
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static struct lpc_spi spi6 =
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{
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.base = SPI6
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};
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static struct rt_spi_bus spi6_bus =
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{
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.parent.user_data = &spi6
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};
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#endif
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#if defined(BSP_USING_SPIBUS7)
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static struct lpc_spi spi7 =
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{
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.base = SPI7
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};
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static struct rt_spi_bus spi7_bus =
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{
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.parent.user_data = &spi7
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};
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#endif
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#if defined(BSP_USING_SPIBUS8)
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static struct lpc_spi spi8 =
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{
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.base = SPI8
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};
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static struct rt_spi_bus spi8_bus =
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{
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.parent.user_data = &spi8
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};
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#endif
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static struct rt_spi_ops lpc_spi_ops =
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{
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.configure = spi_configure,
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.xfer = spixfer
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};
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int rt_hw_spi_init(void)
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{
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#if defined(BSP_USING_SPIBUS0)
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CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
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RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn);
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spi0.cfg = RT_NULL;
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rt_spi_bus_register(&spi0_bus, "spi0", &lpc_spi_ops);
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#endif
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#if defined(BSP_USING_SPIBUS1)
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CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1);
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RESET_PeripheralReset(kFC1_RST_SHIFT_RSTn);
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spi1.cfg = RT_NULL;
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rt_spi_bus_register(&spi1_bus, "spi1", &lpc_spi_ops);
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#endif
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#if defined(BSP_USING_SPIBUS2)
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CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
|
||
|
|
RESET_PeripheralReset(kFC2_RST_SHIFT_RSTn);
|
||
|
|
spi2.cfg = RT_NULL;
|
||
|
|
rt_spi_bus_register(&spi2_bus, "spi2", &lpc_spi_ops);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(BSP_USING_SPIBUS3)
|
||
|
|
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3);
|
||
|
|
RESET_PeripheralReset(kFC3_RST_SHIFT_RSTn);
|
||
|
|
spi3.cfg = RT_NULL;
|
||
|
|
rt_spi_bus_register(&spi3_bus, "spi3", &lpc_spi_ops);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(BSP_USING_SPIBUS4)
|
||
|
|
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
|
||
|
|
RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
|
||
|
|
spi4.cfg = RT_NULL;
|
||
|
|
rt_spi_bus_register(&spi4_bus, "spi4", &lpc_spi_ops);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(BSP_USING_SPIBUS5)
|
||
|
|
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5);
|
||
|
|
RESET_PeripheralReset(kFC5_RST_SHIFT_RSTn);
|
||
|
|
spi5.cfg = RT_NULL;
|
||
|
|
rt_spi_bus_register(&spi5_bus, "spi5", &lpc_spi_ops);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(BSP_USING_SPIBUS6)
|
||
|
|
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM6);
|
||
|
|
RESET_PeripheralReset(kFC6_RST_SHIFT_RSTn);
|
||
|
|
spi6.cfg = RT_NULL;
|
||
|
|
rt_spi_bus_register(&spi6_bus, "spi6", &lpc_spi_ops);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(BSP_USING_SPIBUS7)
|
||
|
|
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM7);
|
||
|
|
RESET_PeripheralReset(kFC7_RST_SHIFT_RSTn);
|
||
|
|
spi7.cfg = RT_NULL;
|
||
|
|
rt_spi_bus_register(&spi7_bus, "spi7", &lpc_spi_ops);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(BSP_USING_SPIBUS8)
|
||
|
|
CLOCK_AttachClk(kMAIN_CLK_to_HSLSPI);
|
||
|
|
RESET_PeripheralReset(kHSLSPI_RST_SHIFT_RSTn);
|
||
|
|
spi8.cfg = RT_NULL;
|
||
|
|
spi8.spi_rst = kHSLSPI_RST_SHIFT_RSTn;
|
||
|
|
rt_spi_bus_register(&spi8_bus, "spi8", &lpc_spi_ops);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
INIT_BOARD_EXPORT(rt_hw_spi_init);
|
||
|
|
|
||
|
|
#endif
|