248 lines
6.4 KiB
C
248 lines
6.4 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-04-17 WangBing the first version.
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* 2019-04-22 tyustli add imxrt series support
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*
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*/
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#include <rtthread.h>
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#ifdef BSP_USING_HWTIMER
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#define LOG_TAG "drv.hwtimer"
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#include <drv_log.h>
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#include <rtdevice.h>
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#include "drv_hwtimer.h"
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#include "fsl_gpt.h"
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#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
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#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
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#endif
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/* Select IPG Clock as PERCLK_CLK clock source */
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#define EXAMPLE_GPT_CLOCK_SOURCE_SELECT (0U)
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/* Clock divider for PERCLK_CLK clock source */
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#define EXAMPLE_GPT_CLOCK_DIVIDER_SELECT (5U)
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/* Get source clock for GPT driver (GPT prescaler = 6) */
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#ifdef SOC_IMXRT1170_SERIES
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#undef EXAMPLE_GPT_CLOCK_DIVIDER_SELECT
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#define EXAMPLE_GPT_CLOCK_DIVIDER_SELECT (2U)
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// 1170 use this root directly, we have already divide this clk, can read it directly
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#define EXAMPLE_GPT_CLK_FREQ (CLOCK_GetRootClockFreq(kCLOCK_Root_Gpt1))
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#else
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#define EXAMPLE_GPT_CLK_FREQ (CLOCK_GetFreq(kCLOCK_IpgClk) / (EXAMPLE_GPT_CLOCK_DIVIDER_SELECT + 1U))
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#endif
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static void NVIC_Configuration(void)
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{
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#ifdef BSP_USING_HWTIMER1
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EnableIRQ(GPT1_IRQn);
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#endif
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#ifdef BSP_USING_HWTIMER2
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EnableIRQ(GPT2_IRQn);
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#endif
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}
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static rt_err_t imxrt_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args)
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{
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rt_err_t err = RT_EOK;
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GPT_Type *hwtimer_dev;
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hwtimer_dev = (GPT_Type *)timer->parent.user_data;
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RT_ASSERT(timer != RT_NULL);
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switch (cmd)
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{
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case HWTIMER_CTRL_FREQ_SET:
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{
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uint32_t clk;
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uint32_t pre;
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clk = EXAMPLE_GPT_CLK_FREQ;
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pre = clk / *((uint32_t *)args) - 1;
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GPT_SetClockDivider(hwtimer_dev, pre);
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}
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break;
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default:
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err = -RT_ENOSYS;
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break;
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}
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return err;
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}
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static rt_uint32_t imxrt_hwtimer_count_get(rt_hwtimer_t *timer)
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{
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rt_uint32_t CurrentTimer_Count;
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GPT_Type *hwtimer_dev;
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hwtimer_dev = (GPT_Type *)timer->parent.user_data;
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RT_ASSERT(timer != RT_NULL);
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CurrentTimer_Count = GPT_GetCurrentTimerCount(hwtimer_dev);
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return CurrentTimer_Count;
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}
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static void imxrt_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
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{
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GPT_Type *hwtimer_dev;
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gpt_config_t gptConfig;
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hwtimer_dev = (GPT_Type *)timer->parent.user_data;
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RT_ASSERT(timer != RT_NULL);
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if (state == 1)
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{
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#ifdef SOC_IMXRT1170_SERIES
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#ifdef BSP_USING_HWTIMER1
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/*Clock setting for GPT*/
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CLOCK_SetRootClockMux(kCLOCK_Root_Gpt1, EXAMPLE_GPT_CLOCK_SOURCE_SELECT);
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CLOCK_SetRootClockDiv(kCLOCK_Root_Gpt1, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT);
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#endif
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#ifdef BSP_USING_HWTIMER2
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/*Clock setting for GPT*/
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CLOCK_SetRootClockMux(kCLOCK_Root_Gpt2, EXAMPLE_GPT_CLOCK_SOURCE_SELECT);
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CLOCK_SetRootClockDiv(kCLOCK_Root_Gpt2, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT);
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#endif
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#else
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/*Clock setting for GPT*/
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CLOCK_SetMux(kCLOCK_PerclkMux, EXAMPLE_GPT_CLOCK_SOURCE_SELECT);
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CLOCK_SetDiv(kCLOCK_PerclkDiv, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT);
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#endif
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/* Initialize GPT module by default config */
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GPT_GetDefaultConfig(&gptConfig);
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GPT_Init(hwtimer_dev, &gptConfig);
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}
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}
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static rt_err_t imxrt_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
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{
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GPT_Type *hwtimer_dev;
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hwtimer_dev = (GPT_Type *)timer->parent.user_data;
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RT_ASSERT(timer != RT_NULL);
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hwtimer_dev->CR |= (mode != HWTIMER_MODE_PERIOD) ? GPT_CR_FRR_MASK : 0U;
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GPT_SetOutputCompareValue(hwtimer_dev, kGPT_OutputCompare_Channel1, cnt);
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GPT_EnableInterrupts(hwtimer_dev, kGPT_OutputCompare1InterruptEnable);
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NVIC_Configuration();
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GPT_StartTimer(hwtimer_dev);
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return RT_EOK;
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}
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static void imxrt_hwtimer_stop(rt_hwtimer_t *timer)
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{
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GPT_Type *hwtimer_dev;
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hwtimer_dev = (GPT_Type *)timer->parent.user_data;
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RT_ASSERT(timer != RT_NULL);
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GPT_StopTimer(hwtimer_dev);
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}
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static const struct rt_hwtimer_ops imxrt_hwtimer_ops =
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{
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.init = imxrt_hwtimer_init,
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.start = imxrt_hwtimer_start,
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.stop = imxrt_hwtimer_stop,
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.count_get = imxrt_hwtimer_count_get,
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.control = imxrt_hwtimer_control,
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};
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static const struct rt_hwtimer_info imxrt_hwtimer_info =
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{
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25000000, /* the maximum count frequency can be set */
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6103, /* the minimum count frequency can be set */
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0xFFFFFFFF,
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HWTIMER_CNTMODE_UP,
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};
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#ifdef BSP_USING_HWTIMER1
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static rt_hwtimer_t GPT_timer1;
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#endif /*BSP_USING_HWTIMER1*/
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#ifdef BSP_USING_HWTIMER2
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static rt_hwtimer_t GPT_timer2;
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#endif
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int rt_hw_hwtimer_init(void)
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{
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int ret = RT_EOK;
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#ifdef BSP_USING_HWTIMER1
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GPT_timer1.info = &imxrt_hwtimer_info;
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GPT_timer1.ops = &imxrt_hwtimer_ops;
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ret = rt_device_hwtimer_register(&GPT_timer1, "gpt1", GPT1);
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if (ret != RT_EOK)
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{
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LOG_E("gpt1 register failed\n");
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}
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#endif
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#ifdef BSP_USING_HWTIMER2
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GPT_timer2.info = &imxrt_hwtimer_info;
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GPT_timer2.ops = &imxrt_hwtimer_ops;
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ret = rt_device_hwtimer_register(&GPT_timer2, "gpt2", GPT2);
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if (ret != RT_EOK)
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{
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LOG_E("gpt1 register failed\n");
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}
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#endif
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return ret;
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}
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#ifdef BSP_USING_HWTIMER1
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void GPT1_IRQHandler(void)
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{
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if (GPT_GetStatusFlags(GPT1, kGPT_OutputCompare1Flag) != 0)
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{
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GPT_ClearStatusFlags(GPT1, kGPT_OutputCompare1Flag);
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rt_device_hwtimer_isr(&GPT_timer1);
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}
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/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M7F Store immediate overlapping
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exception return operation might vector to incorrect interrupt */
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#if defined __CORTEX_M && (__CORTEX_M == 4U || __CORTEX_M == 7U)
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__DSB();
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#endif
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}
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#endif /*BSP_USING_HWTIMER1*/
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#ifdef BSP_USING_HWTIMER2
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void GPT2_IRQHandler(void)
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{
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if (GPT_GetStatusFlags(GPT2, kGPT_OutputCompare1Flag) != 0)
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{
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GPT_ClearStatusFlags(GPT2, kGPT_OutputCompare1Flag);
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rt_device_hwtimer_isr(&GPT_timer2);
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}
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/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M7F Store immediate overlapping
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exception return operation might vector to incorrect interrupt */
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#if defined __CORTEX_M && (__CORTEX_M == 4U || __CORTEX_M == 7U)
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__DSB();
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#endif
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}
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#endif /*BSP_USING_HWTIMER2*/
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INIT_DEVICE_EXPORT(rt_hw_hwtimer_init);
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#endif /* BSP_USING_HWTIMER */
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