Shell fe2b124345 feat: arm64 ASID support ... Support for ARM64 ASID to enhance virtual memory management efficiency by reducing the need for TLB flushes during address space switches. These changes improve performance especially for multi-process systems. Changes: - Added `ARCH_USING_ASID` configuration in `libcpu/aarch64/Kconfig`. - Defined ASID-related constants in `mmu.h`. - Updated `TLBI_ARG` macro to include ASID manipulation. - Implemented ASID allocation mechanism with spinlock synchronization. - Enhanced TLB invalidation to support ASID-specific operations. - Modified `rt_hw_aspace_switch` to use ASIDs when switching address spaces. - Adjusted debug logging and function documentation to reflect ASID usage. - Refactored AArch64 MMU and TLB handling for ASID integration. Signed-off-by: Shell <smokewood@qq.com>		2024-11-24 13:44:34 -05:00
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common	feat: arm64 ASID support	2024-11-24 13:44:34 -05:00
cortex-a	[lwp][vdso] Add VDSO functionality under the aarch64 architecture (#9176)	2024-07-15 17:58:29 +08:00
.gitignore	AArch64: support public linker scripts (#7831)	2023-07-25 21:31:44 +08:00
SConscript	[smart] fixup of lwp recycling and mm varea (#8206)	2023-11-02 20:23:11 +08:00
link.lds.S	[BSP][Phytium] add support for mainbranch cherryusb (xhci host + pusb2 device/host)	2024-08-27 22:06:13 -04:00