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c802fcdcf8
WCH CH569W-R0-1v0 evt board bsp port, first version dev/test under Ubuntu 20.04 toolchain from MounRiver_Studio_Community_Linux_x64_V120 tested drivers : SysTick, gpio, gpio interrupt, uart1 (RX interrupt, TX polling) libcpu/risc-v/SConscript : group includes rtconfig.CPU only if folder exists libcpu/risc-v/common/cpuport.c/rt_hw_context_switch_interrupt() : make it RT_WEAK for customization
16 lines
254 B
Plaintext
16 lines
254 B
Plaintext
config SOC_RISCV_FAMILY_CH32
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bool
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config SOC_RISCV_SERIES_CH32V103
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bool
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select ARCH_RISCV
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select SOC_RISCV_FAMILY_CH32
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config SOC_FAMILY_CH56X
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bool
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select ARCH_RISCV
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config SOC_SERIES_CH569
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bool
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select SOC_FAMILY_CH56X
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