332 lines
13 KiB
C
332 lines
13 KiB
C
/**
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*******************************************************************************
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* @file hc32f4a0_i2s.h
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* @brief This file contains all the functions prototypes of the I2S driver
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* library.
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@verbatim
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Change Logs:
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Date Author Notes
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2020-06-12 Yangjp First version
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#ifndef __HC32F4A0_I2S_H__
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#define __HC32F4A0_I2S_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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/**
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* @addtogroup HC32F4A0_DDL_Driver
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* @{
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*/
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/**
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* @addtogroup DDL_I2S
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* @{
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*/
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#if (DDL_I2S_ENABLE == DDL_ON)
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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* @defgroup I2S_Global_Types I2S Global Types
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* @{
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*/
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/**
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* @brief I2S Init structure definition
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*/
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typedef struct
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{
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uint32_t u32ClockSrc; /*!< Specifies the clock source of I2S.
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This parameter can be a value of @ref I2S_Clock_Source */
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uint32_t u32Mode; /*!< Specifies the master/slave mode of I2S.
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This parameter can be a value of @ref I2S_Mode */
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uint32_t u32ComProtocol; /*!< Specifies the communication protocol of I2S.
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This parameter can be a value of @ref I2S_Com_Protocol */
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uint32_t u32TransMode; /*!< Specifies the transmission mode for the I2S communication.
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This parameter can be a value of @ref I2S_Trans_Mode */
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uint32_t u32AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
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This parameter can be a value of @ref I2S_Audio_Frequency */
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uint32_t u32ChLen; /*!< Specifies the channel length for the I2S communication.
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This parameter can be a value of @ref I2S_Channel_Length */
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uint32_t u32DataLen; /*!< Specifies the data length for the I2S communication.
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This parameter can be a value of @ref I2S_Data_Length */
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uint32_t u32MCKOutput; /*!< Specifies the validity of the MCK output for I2S.
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This parameter can be a value of @ref I2S_MCK_Output */
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uint32_t u32TransFIFOLevel; /*!< Specifies the level of transfer FIFO.
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This parameter can be a value of @ref I2S_Trans_Level */
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uint32_t u32ReceiveFIFOLevel; /*!< Specifies the level of receive FIFO.
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This parameter can be a value of @ref I2S_Receive_Level */
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} stc_i2s_init_t;
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/**
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* @}
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*/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup I2S_Global_Macros I2S Global Macros
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* @{
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*/
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/**
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* @defgroup I2S_Clock_Source I2S Clock Source
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* @{
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*/
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#define I2S_CLK_SRC_PLL (I2S_CTRL_I2SPLLSEL) /*!< Internal PLL Clock */
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#define I2S_CLK_SRC_EXT (I2S_CTRL_CLKSEL) /*!< External Clock */
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/**
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* @}
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*/
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/**
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* @defgroup I2S_Mode I2S Mode
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* @{
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*/
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#define I2S_MD_MASTER (0UL) /*!< Master mode */
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#define I2S_MD_SLAVE (I2S_CTRL_WMS) /*!< Slave mode */
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/**
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* @}
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*/
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/**
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* @defgroup I2S_Com_Protocol I2S Communication Protocol
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* @{
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*/
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#define I2S_COM_PROTOCOL_PHILLIPS (0UL) /*!< Phillips protocol */
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#define I2S_COM_PROTOCOL_MSB (I2S_CFGR_I2SSTD_0) /*!< MSB justified protocol */
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#define I2S_COM_PROTOCOL_LSB (I2S_CFGR_I2SSTD_1) /*!< LSB justified protocol */
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#define I2S_COM_PROTOCOL_PCM_SHORT (I2S_CFGR_I2SSTD) /*!< PCM short-frame protocol */
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#define I2S_COM_PROTOCOL_PCM_LONG (I2S_CFGR_I2SSTD | I2S_CFGR_PCMSYNC) /*!< PCM long-frame protocol */
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/**
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* @}
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*/
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/**
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* @defgroup I2S_Trans_Mode I2S Transfer Mode
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* @{
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*/
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#define I2S_TRANS_MD_HALF_DUPLEX_RX (0UL) /*!< Receive only and half duplex mode */
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#define I2S_TRANS_MD_HALF_DUPLEX_TX (I2S_CTRL_SDOE) /*!< Send only and half duplex mode */
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#define I2S_TRANS_MD_FULL_DUPLEX (I2S_CTRL_DUPLEX | I2S_CTRL_SDOE) /*!< Full duplex mode */
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/**
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* @}
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*/
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/**
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* @defgroup I2S_Audio_Frequency I2S Audio Frequency
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* @{
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*/
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#define I2S_AUDIO_FREQ_192K (192000UL) /*!< FS = 192000Hz */
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#define I2S_AUDIO_FREQ_96K (96000UL) /*!< FS = 96000Hz */
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#define I2S_AUDIO_FREQ_48K (48000UL) /*!< FS = 48000Hz */
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#define I2S_AUDIO_FREQ_44K (44100UL) /*!< FS = 44100Hz */
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#define I2S_AUDIO_FREQ_32K (32000UL) /*!< FS = 32000Hz */
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#define I2S_AUDIO_FREQ_22K (22050UL) /*!< FS = 22050Hz */
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#define I2S_AUDIO_FREQ_16K (16000UL) /*!< FS = 16000Hz */
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#define I2S_AUDIO_FREQ_8K (8000UL) /*!< FS = 8000Hz */
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#define I2S_AUDIO_FREQ_DEFAULT (2UL)
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/**
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* @}
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*/
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/**
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* @defgroup I2S_Channel_Length I2S Channel Length
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* @{
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*/
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#define I2S_CH_LEN_16BIT (0UL) /*!< Channel length is 16bits */
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#define I2S_CH_LEN_32BIT (I2S_CFGR_CHLEN) /*!< Channel length is 32bits */
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/**
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* @}
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*/
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/**
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* @defgroup I2S_Data_Length I2S Data Length
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* @{
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*/
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#define I2S_DATA_LEN_16BIT (0UL) /*!< Transfer data length is 16bits */
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#define I2S_DATA_LEN_24BIT (I2S_CFGR_DATLEN_0) /*!< Transfer data length is 24bits */
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#define I2S_DATA_LEN_32BIT (I2S_CFGR_DATLEN_1) /*!< Transfer data length is 32bits */
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/**
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* @}
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*/
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/**
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* @defgroup I2S_MCK_Output I2S MCK Output
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* @{
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*/
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#define I2S_MCK_OUTPUT_DISABLE (0UL) /*!< Disable the drive clock(MCK) output */
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#define I2S_MCK_OUTPUT_ENABLE (I2S_CTRL_MCKOE) /*!< Enable the drive clock(MCK) output */
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/**
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* @}
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*/
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/**
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* @defgroup I2S_Trans_Level I2S Transfer Level
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* @{
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*/
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#define I2S_TRANS_LVL0 (0x00UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 0 */
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#define I2S_TRANS_LVL1 (0x01UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 1 */
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#define I2S_TRANS_LVL2 (0x02UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 2 */
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#define I2S_TRANS_LVL3 (0x03UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 3 */
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#define I2S_TRANS_LVL4 (0x04UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 4 */
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/**
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* @}
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*/
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/**
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* @defgroup I2S_Receive_Level I2S Receive Level
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* @{
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*/
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#define I2S_RECEIVE_LVL0 (0x00UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 0 */
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#define I2S_RECEIVE_LVL1 (0x01UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 1 */
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#define I2S_RECEIVE_LVL2 (0x02UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 2 */
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#define I2S_RECEIVE_LVL3 (0x03UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 3 */
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#define I2S_RECEIVE_LVL4 (0x04UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 4 */
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/**
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* @}
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*/
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/**
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* @defgroup I2S_Com_Func I2S Communication Function
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* @{
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*/
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#define I2S_FUNC_TXE (I2S_CTRL_TXE) /*!< Transfer function */
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#define I2S_FUNC_RXE (I2S_CTRL_RXE) /*!< Receive function */
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#define I2S_FUNC_ALL (I2S_FUNC_TXE | I2S_FUNC_RXE)
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/**
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* @}
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*/
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/**
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* @defgroup I2S_Reset_Type I2S Reset Type
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* @{
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*/
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#define I2S_RST_TYPE_SW (I2S_CTRL_SRST) /*!< I2S software reset */
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#define I2S_RST_TYPE_CODEC (I2S_CTRL_CODECRC) /*!< Reset codec of I2S */
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#define I2S_RST_TYPE_FIFO (I2S_CTRL_FIFOR) /*!< Reset FIFO of I2S */
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#define I2S_RST_TYPE_ALL (I2S_RST_TYPE_SW | I2S_RST_TYPE_CODEC | I2S_RST_TYPE_FIFO)
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/**
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* @}
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*/
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/**
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* @defgroup I2S_Interrupt I2S Interrupt
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* @{
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*/
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#define I2S_INT_TX (I2S_CTRL_TXIE) /*!< Transfer interrupt */
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#define I2S_INT_RX (I2S_CTRL_RXIE) /*!< Receive interrupt */
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#define I2S_INT_ERR (I2S_CTRL_EIE) /*!< Communication error interrupt */
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#define I2S_INT_ALL (I2S_INT_TX | I2S_INT_RX | I2S_INT_ERR)
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/**
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* @}
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*/
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/**
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* @defgroup I2S_Flag I2S Flag
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* @{
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*/
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#define I2S_FLAG_TX_ALARM (I2S_SR_TXBA) /*!< Transfer buffer alarm flag */
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#define I2S_FLAG_RX_ALARM (I2S_SR_RXBA) /*!< Receive buffer alarm flag */
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#define I2S_FLAG_TX_EMPTY (I2S_SR_TXBE) /*!< Transfer buffer empty flag */
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#define I2S_FLAG_TX_FULL (I2S_SR_TXBF) /*!< Transfer buffer full flag */
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#define I2S_FLAG_RX_EMPTY (I2S_SR_RXBE) /*!< Receive buffer empty flag */
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#define I2S_FLAG_RX_FULL (I2S_SR_RXBF) /*!< Receive buffer full flag */
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#define I2S_FLAG_TX_ERR (I2S_ER_TXERR << 16U) /*!< Transfer overflow or underflow flag */
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#define I2S_FLAG_RX_ERR (I2S_ER_RXERR << 16U) /*!< Receive overflow flag */
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#define I2S_FLAG_ALL (I2S_FLAG_TX_ALARM | I2S_FLAG_RX_ALARM | I2S_FLAG_TX_EMPTY | \
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I2S_FLAG_TX_FULL | I2S_FLAG_RX_EMPTY | I2S_FLAG_RX_FULL | \
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I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR)
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#define I2S_CLR_FLAG_ALL (I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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/**
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* @addtogroup I2S_Global_Functions
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* @{
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*/
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/* Initialization and configuration functions */
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void I2S_DeInit(M4_I2S_TypeDef *I2Sx);
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en_result_t I2S_Init(M4_I2S_TypeDef *I2Sx, const stc_i2s_init_t *pstcI2sInit);
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en_result_t I2S_StructInit(stc_i2s_init_t *pstcI2sInit);
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void I2S_SetSWReset(M4_I2S_TypeDef *I2Sx, uint32_t u32ResetType);
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void I2S_SetTransMode(M4_I2S_TypeDef *I2Sx, uint32_t u32Mode);
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void I2S_SetTransFIFOLevel(M4_I2S_TypeDef *I2Sx, uint32_t u32Level);
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void I2S_SetReceiveFIFOLevel(M4_I2S_TypeDef *I2Sx, uint32_t u32Level);
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void I2S_SetComProtocol(M4_I2S_TypeDef *I2Sx, uint32_t u32Protocol);
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en_result_t I2S_SetAudioFreq(M4_I2S_TypeDef *I2Sx, uint32_t u32Freq);
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void I2S_MCKOutputCmd(M4_I2S_TypeDef *I2Sx, en_functional_state_t enNewState);
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void I2S_FuncCmd(M4_I2S_TypeDef* I2Sx, uint32_t u32Func, en_functional_state_t enNewState);
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/* Transfer and receive data functions */
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void I2S_WriteData(M4_I2S_TypeDef *I2Sx, uint32_t u32Data);
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uint32_t I2S_ReadData(const M4_I2S_TypeDef *I2Sx);
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en_result_t I2S_Trans(M4_I2S_TypeDef *I2Sx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout);
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en_result_t I2S_Receive(const M4_I2S_TypeDef *I2Sx, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout);
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en_result_t I2S_TransReceive(M4_I2S_TypeDef *I2Sx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout);
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/* Interrupt and flag management functions */
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void I2S_IntCmd(M4_I2S_TypeDef *I2Sx, uint32_t u32IntType, en_functional_state_t enNewState);
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en_flag_status_t I2S_GetStatus(const M4_I2S_TypeDef *I2Sx, uint32_t u32Flag);
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void I2S_ClearStatus(M4_I2S_TypeDef *I2Sx, uint32_t u32Flag);
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/**
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* @}
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*/
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#endif /* DDL_I2S_ENABLE */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HC32F4A0_I2S_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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