179 lines
5.9 KiB
C
179 lines
5.9 KiB
C
/*
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** ###################################################################
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** Processors: MIMXRT1176AVM8A_cm4
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** MIMXRT1176CVM8A_cm4
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** MIMXRT1176DVMAA_cm4
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**
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** Compilers: Freescale C/C++ for Embedded ARM
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** GNU C Compiler
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** IAR ANSI C/C++ Compiler for ARM
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** Keil ARM C/C++ Compiler
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** MCUXpresso Compiler
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**
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** Reference manual: IMXRT1170RM, Rev 1, 02/2021
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** Version: rev. 1.0, 2020-12-29
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** Build: b210615
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**
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** Abstract:
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** Provides a system configuration function and a global variable that
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** contains the system frequency. It configures the device and initializes
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** the oscillator (PLL) that is part of the microcontroller device.
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2021 NXP
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** All rights reserved.
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**
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 0.1 (2018-03-05)
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** Initial version.
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** - rev. 1.0 (2020-12-29)
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** Update header files to align with IMXRT1170RM Rev.0.
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**
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** ###################################################################
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*/
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/*!
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* @file MIMXRT1176_cm4
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* @version 1.0
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* @date 2021-06-15
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* @brief Device specific configuration file for MIMXRT1176_cm4 (implementation
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* file)
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*
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* Provides a system configuration function and a global variable that contains
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* the system frequency. It configures the device and initializes the oscillator
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* (PLL) that is part of the microcontroller device.
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*/
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#include <stdint.h>
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#include "fsl_device_registers.h"
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/* ----------------------------------------------------------------------------
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-- Core clock
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---------------------------------------------------------------------------- */
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uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
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/* ----------------------------------------------------------------------------
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-- SystemInit()
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---------------------------------------------------------------------------- */
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void SystemInit (void) {
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#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
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#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
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#if defined(__MCUXPRESSO)
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extern uint32_t g_pfnVectors[]; // Vector table defined in startup code
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SCB->VTOR = (uint32_t)g_pfnVectors;
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#endif
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/* Watchdog disable */
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#if (DISABLE_WDOG)
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if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
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{
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WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
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}
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if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
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{
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WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
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}
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if ((RTWDOG3->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
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{
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RTWDOG3->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
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}
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else
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{
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RTWDOG3->CNT = 0xC520U;
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RTWDOG3->CNT = 0xD928U;
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}
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RTWDOG3->TOVAL = 0xFFFF;
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RTWDOG3->CS = (uint32_t) ((RTWDOG3->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
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if ((RTWDOG4->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
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{
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RTWDOG4->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
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}
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else
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{
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RTWDOG4->CNT = 0xC520U;
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RTWDOG4->CNT = 0xD928U;
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}
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RTWDOG4->TOVAL = 0xFFFF;
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RTWDOG4->CS = (uint32_t) ((RTWDOG4->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
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#endif /* (DISABLE_WDOG) */
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/* Disable Systick which might be enabled by bootrom */
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if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
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{
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SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
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}
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/* Initialize Cache */
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/* Enable Code Bus Cache */
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if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK))
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{
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/* set command to invalidate all ways, and write GO bit to initiate command */
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LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_GO_MASK;
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/* Wait until the command completes */
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while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) {
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}
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/* Enable cache, enable write buffer */
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LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
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}
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/* Enable System Bus Cache */
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if (0U == (LMEM->PSCCR & LMEM_PSCCR_ENCACHE_MASK))
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{
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/* set command to invalidate all ways, and write GO bit to initiate command */
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LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_GO_MASK;
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/* Wait until the command completes */
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while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) {
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}
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/* Enable cache, enable write buffer */
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LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK);
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}
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/* Clear bit 13 to its reset value since it might be set by ROM. */
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IOMUXC_GPR->GPR28 &= ~IOMUXC_GPR_GPR28_CACHE_USB_MASK;
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#if defined(ROM_ECC_ENABLED)
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/* When ECC is enabled, SRC->SRSR need to be cleared since only correct SRSR value can trigger ROM ECC preload procedure.
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Save SRSR to SRC->GPR[11] so that application can still check SRSR value from SRC->GPR[11]. */
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SRC->GPR[11] = SRC->SRSR;
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/* clear SRSR */
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SRC->SRSR = 0xFFFFFFFFU;
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#endif
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/* Enable entry to thread mode when divide by zero */
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SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
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__DSB();
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__ISB();
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SystemInitHook();
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}
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/* ----------------------------------------------------------------------------
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-- SystemCoreClockUpdate()
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---------------------------------------------------------------------------- */
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void SystemCoreClockUpdate (void) {
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/* TBD */
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}
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/* ----------------------------------------------------------------------------
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-- SystemInitHook()
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---------------------------------------------------------------------------- */
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__attribute__ ((weak)) void SystemInitHook (void) {
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/* Void implementation of the weak function. */
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}
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