99 lines
4.1 KiB
Plaintext
99 lines
4.1 KiB
Plaintext
/*
|
|
** ###################################################################
|
|
** Processors: MIMXRT1176AVM8A_cm4
|
|
** MIMXRT1176CVM8A_cm4
|
|
** MIMXRT1176DVMAA_cm4
|
|
**
|
|
** Compiler: IAR ANSI C/C++ Compiler for ARM
|
|
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
|
|
** Version: rev. 1.1, 2022-04-02
|
|
** Build: b220402
|
|
**
|
|
** Abstract:
|
|
** Linker file for the IAR ANSI C/C++ Compiler for ARM
|
|
**
|
|
** Copyright 2016 Freescale Semiconductor, Inc.
|
|
** Copyright 2016-2022 NXP
|
|
** All rights reserved.
|
|
**
|
|
** SPDX-License-Identifier: BSD-3-Clause
|
|
**
|
|
** http: www.nxp.com
|
|
** mail: support@nxp.com
|
|
**
|
|
** ###################################################################
|
|
*/
|
|
|
|
define symbol m_interrupts_start = 0x1FFE0000;
|
|
define symbol m_interrupts_end = 0x1FFE03FF;
|
|
|
|
define symbol m_text_start = 0x1FFE0400;
|
|
define symbol m_text_end = 0x1FFFFFFF;
|
|
|
|
define symbol m_data_start = 0x20000000;
|
|
define symbol m_data_end = 0x2001FFFF;
|
|
|
|
define symbol m_data2_start = 0x20240000;
|
|
define symbol m_data2_end = 0x202BFFFF;
|
|
|
|
define symbol m_data3_start = 0x80000000;
|
|
define symbol m_data3_end = 0x82FFFFFF;
|
|
|
|
define symbol m_ncache_start = 0x83000000;
|
|
define symbol m_ncache_end = 0x83FFFFFF;
|
|
|
|
define exported symbol __NCACHE_REGION_START = m_ncache_start;
|
|
define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1;
|
|
|
|
/* Sizes */
|
|
if (isdefinedsymbol(__stack_size__)) {
|
|
define symbol __size_cstack__ = __stack_size__;
|
|
} else {
|
|
define symbol __size_cstack__ = 0x0400;
|
|
}
|
|
|
|
if (isdefinedsymbol(__heap_size__)) {
|
|
define symbol __size_heap__ = __heap_size__;
|
|
} else {
|
|
define symbol __size_heap__ = 0x0400;
|
|
}
|
|
|
|
define exported symbol __VECTOR_TABLE = m_interrupts_start;
|
|
define exported symbol __VECTOR_RAM = m_interrupts_start;
|
|
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
|
|
|
|
define memory mem with size = 4G;
|
|
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
|
|
| mem:[from m_text_start to m_text_end];
|
|
define region DATA_region = mem:[from m_data_start to m_data_end];
|
|
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
|
|
define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__];
|
|
define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end];
|
|
define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
|
|
|
|
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
|
define block HEAP with alignment = 8, size = __size_heap__ { };
|
|
define block RW { first readwrite, section m_usb_dma_init_data };
|
|
define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data };
|
|
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
|
|
define block QACCESS_CODE { section CodeQuickAccess };
|
|
define block QACCESS_DATA { section DataQuickAccess };
|
|
|
|
initialize by copy { readwrite, section .textrw, section CodeQuickAccess, section DataQuickAccess };
|
|
do not initialize { section .noinit };
|
|
|
|
place at address mem: m_interrupts_start { readonly section .intvec };
|
|
|
|
place in TEXT_region { readonly };
|
|
place in DATA3_region { block RW };
|
|
place in DATA3_region { block ZI };
|
|
if (isdefinedsymbol(__heap_noncacheable__)) {
|
|
place in NCACHE_region { last block HEAP };
|
|
} else {
|
|
place in DATA3_region { last block HEAP };
|
|
}
|
|
place in TEXT_region { block QACCESS_CODE };
|
|
place in CSTACK_region { block CSTACK };
|
|
place in NCACHE_region { block NCACHE_VAR };
|
|
place in DATA_region { block QACCESS_DATA };
|