251 lines
14 KiB
C
251 lines
14 KiB
C
/*!
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\file gd32f10x_dac.h
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\brief definitions for the DAC
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\version 2014-12-26, V1.0.0, firmware for GD32F10x
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\version 2017-06-20, V2.0.0, firmware for GD32F10x
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\version 2018-07-31, V2.1.0, firmware for GD32F10x
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F10X_DAC_H
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#define GD32F10X_DAC_H
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#include "gd32f10x.h"
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/* DACx(x=0,1) definitions */
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#define DAC DAC_BASE
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#define DAC0 0U
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#define DAC1 1U
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/* registers definitions */
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#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */
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#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */
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#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */
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#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */
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#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */
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#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */
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#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */
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#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */
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#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */
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#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */
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#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */
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#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */
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#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */
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/* bits definitions */
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/* DAC_CTL */
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#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */
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#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/off bit */
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#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */
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#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */
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#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */
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#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */
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#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */
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#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */
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#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */
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#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */
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#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */
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#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */
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#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */
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#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */
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/* DAC_SWT */
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#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */
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#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */
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/* DAC0_R12DH */
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#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */
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/* DAC0_L12DH */
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#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */
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/* DAC0_R8DH */
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#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */
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/* DAC1_R12DH */
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#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */
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/* DAC1_L12DH */
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#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */
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/* DAC1_R8DH */
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#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */
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/* DACC_R12DH */
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#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */
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#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */
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/* DACC_L12DH */
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#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */
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#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */
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/* DACC_R8DH */
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#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */
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#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */
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/* DAC0_DO */
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#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */
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/* DAC1_DO */
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#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */
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/* constants definitions */
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/* DAC trigger source */
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#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
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#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */
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#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
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#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */
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#elif defined(GD32F10X_CL)
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#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */
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#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
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#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */
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#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */
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#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */
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#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */
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#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */
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#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */
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/* DAC noise wave mode */
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#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
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#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */
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#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */
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#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */
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/* DAC noise wave bit width */
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#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
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#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */
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#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */
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#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */
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#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */
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#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */
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#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */
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#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */
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#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */
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#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */
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#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */
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#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */
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#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */
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/* unmask LFSR bits in DAC LFSR noise mode */
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#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */
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#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */
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#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */
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#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */
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#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */
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#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */
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#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */
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#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */
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#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */
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#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
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#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
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#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
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/* DAC data alignment */
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#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
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#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */
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#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */
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#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */
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/* triangle amplitude in DAC triangle noise mode */
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#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */
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#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */
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#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */
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#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */
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#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */
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#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */
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#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */
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#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */
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#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */
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#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
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#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
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#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
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/* function declarations */
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/* initialization functions */
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/* deinitialize DAC */
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void dac_deinit(void);
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/* enable DAC */
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void dac_enable(uint32_t dac_periph);
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/* disable DAC */
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void dac_disable(uint32_t dac_periph);
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/* enable DAC DMA */
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void dac_dma_enable(uint32_t dac_periph);
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/* disable DAC DMA */
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void dac_dma_disable(uint32_t dac_periph);
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/* enable DAC output buffer */
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void dac_output_buffer_enable(uint32_t dac_periph);
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/* disable DAC output buffer */
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void dac_output_buffer_disable(uint32_t dac_periph);
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/* get the last data output value */
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uint16_t dac_output_value_get(uint32_t dac_periph);
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/* set DAC data holding register value */
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void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data);
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/* DAC trigger configuration */
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/* enable DAC trigger */
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void dac_trigger_enable(uint32_t dac_periph);
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/* disable DAC trigger */
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void dac_trigger_disable(uint32_t dac_periph);
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/* configure DAC trigger source */
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void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource);
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/* enable DAC software trigger */
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void dac_software_trigger_enable(uint32_t dac_periph);
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/* disable DAC software trigger */
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void dac_software_trigger_disable(uint32_t dac_periph);
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/* DAC wave mode configuration */
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/* configure DAC wave mode */
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void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode);
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/* configure DAC wave bit width */
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void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width);
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/* configure DAC LFSR noise mode */
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void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits);
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/* configure DAC triangle noise mode */
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void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude);
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/* DAC concurrent mode configuration */
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/* enable DAC concurrent mode */
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void dac_concurrent_enable(void);
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/* disable DAC concurrent mode */
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void dac_concurrent_disable(void);
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/* enable DAC concurrent software trigger */
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void dac_concurrent_software_trigger_enable(void);
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/* disable DAC concurrent software trigger */
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void dac_concurrent_software_trigger_disable(void);
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/* enable DAC concurrent buffer function */
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void dac_concurrent_output_buffer_enable(void);
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/* disable DAC concurrent buffer function */
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void dac_concurrent_output_buffer_disable(void);
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/* set DAC concurrent mode data holding register value */
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void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1);
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#endif /* GD32F10X_DAC_H */
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