Grissiom f51bce3fed add rm48x50 bsp and libcpu ... We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.		2013-05-24 22:55:13 +08:00
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AT91SAM7S	convert end of line	2013-01-08 05:05:02 -08:00
AT91SAM7X	update AT91SAM7X: Modify the interrupt interface implementations.	2013-03-31 17:43:09 +08:00
at91sam926x	Use SRAM as EMAC transmit buffer, to avoid the underrun error, especially in the large amount of data communication.	2013-04-08 21:57:24 +08:00
common	convert end of line	2013-01-08 05:05:02 -08:00
cortex-m0	port stm32f0x to gcc.	2013-02-20 22:03:31 +08:00
cortex-m3	code cleanup for interrupt description	2013-03-26 08:52:33 +08:00
cortex-m4	convert end of line	2013-01-08 05:05:02 -08:00
lpc24xx	update LPC2478: Modify the interrupt interface implementations.	2013-03-31 18:25:51 +08:00
lpc214x	update LPC214X: Modify the interrupt interface implementations.	2013-03-31 17:58:26 +08:00
rm48x50	add rm48x50 bsp and libcpu	2013-05-24 22:55:13 +08:00
s3c24x0	update mini2440: Modify the interrupt interface implementations.	2013-03-31 17:30:30 +08:00
s3c44b0	convert end of line	2013-01-08 05:05:02 -08:00
sep4020	fixed compiling error related to the RT_USING_INTERRUPT_INFO in mini4020	2013-04-10 00:49:18 +08:00