mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2025-01-29 10:00:25 +08:00
f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
68 lines
2.1 KiB
Batchfile
68 lines
2.1 KiB
Batchfile
/*----------------------------------------------------------------------------*/
|
|
/* sys_link.cmd */
|
|
/* */
|
|
/* (c) Texas Instruments 2009-2013, All rights reserved. */
|
|
/* */
|
|
/*----------------------------------------------------------------------------*/
|
|
/* USER CODE BEGIN (7) */
|
|
/* USER CODE END */
|
|
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* Linker Settings */
|
|
|
|
--retain="*(.intvecs)"
|
|
|
|
/* USER CODE BEGIN (8) */
|
|
/* USER CODE END */
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* Memory Map */
|
|
|
|
MEMORY
|
|
{
|
|
VECTORS (X) : origin=0x00000000 length=0x00000020
|
|
FLASH0 (RX) : origin=0x00000020 length=0x0017FFE0
|
|
FLASH1 (RX) : origin=0x00180000 length=0x00180000
|
|
STACKS (RW) : origin=0x08000000 length=0x00001500
|
|
RAM (RW) : origin=0x08001500 length=0x0003eaff
|
|
|
|
/* USER CODE BEGIN (9) */
|
|
/* USER CODE END */
|
|
}
|
|
|
|
/* USER CODE BEGIN (10) */
|
|
/* USER CODE END */
|
|
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* Section Configuration */
|
|
|
|
SECTIONS
|
|
{
|
|
.intvecs : {} > VECTORS
|
|
.text : {} > FLASH0 | FLASH1
|
|
.const : {} > FLASH0 | FLASH1
|
|
.cinit : {} > FLASH0 | FLASH1
|
|
.pinit : {} > FLASH0 | FLASH1
|
|
.bss : {} > RAM
|
|
.data : {} > RAM
|
|
.sysmem : {} > RAM
|
|
|
|
|
|
/* USER CODE BEGIN (11) */
|
|
/* USER CODE END */
|
|
}
|
|
|
|
/* USER CODE BEGIN (12) */
|
|
/* USER CODE END */
|
|
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* Misc */
|
|
|
|
/* USER CODE BEGIN (13) */
|
|
/* USER CODE END */
|
|
/*----------------------------------------------------------------------------*/
|
|
|