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f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
160 lines
5.4 KiB
C
160 lines
5.4 KiB
C
/** @file reg_system.h
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* @brief System Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* .
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* which are relevant for the System driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_SYSTEM_H__
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#define __REG_SYSTEM_H__
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#include "sys_common.h"
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#include "gio.h"
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/* System Register Frame 1 Definition */
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/** @struct systemBase1
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* @brief System Register Frame 1 Definition
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*
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* This type is used to access the System 1 Registers.
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*/
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/** @typedef systemBASE1_t
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* @brief System Register Frame 1 Type Definition
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*
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* This type is used to access the System 1 Registers.
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*/
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typedef volatile struct systemBase1
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{
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uint32 SYSPC1; /* 0x0000 */
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uint32 SYSPC2; /* 0x0004 */
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uint32 SYSPC3; /* 0x0008 */
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uint32 SYSPC4; /* 0x000C */
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uint32 SYSPC5; /* 0x0010 */
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uint32 SYSPC6; /* 0x0014 */
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uint32 SYSPC7; /* 0x0018 */
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uint32 SYSPC8; /* 0x001C */
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uint32 SYSPC9; /* 0x0020 */
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uint32 SSWPLL1; /* 0x0024 */
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uint32 SSWPLL2; /* 0x0028 */
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uint32 SSWPLL3; /* 0x002C */
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uint32 CSDIS; /* 0x0030 */
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uint32 CSDISSET; /* 0x0034 */
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uint32 CSDISCLR; /* 0x0038 */
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uint32 CDDIS; /* 0x003C */
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uint32 CDDISSET; /* 0x0040 */
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uint32 CDDISCLR; /* 0x0044 */
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uint32 GHVSRC; /* 0x0048 */
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uint32 VCLKASRC; /* 0x004C */
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uint32 RCLKSRC; /* 0x0050 */
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uint32 CSVSTAT; /* 0x0054 */
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uint32 MSTGCR; /* 0x0058 */
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uint32 MINITGCR; /* 0x005C */
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uint32 MSINENA; /* 0x0060 */
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uint32 MSTFAIL; /* 0x0064 */
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uint32 MSTCGSTAT; /* 0x0068 */
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uint32 MINISTAT; /* 0x006C */
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uint32 PLLCTL1; /* 0x0070 */
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uint32 PLLCTL2; /* 0x0074 */
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uint32 UERFLAG; /* 0x0078 */
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uint32 DIEIDL; /* 0x007C */
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uint32 DIEIDH; /* 0x0080 */
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uint32 VRCTL; /* 0x0084 */
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uint32 LPOMONCTL; /* 0x0088 */
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uint32 CLKTEST; /* 0x008C */
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uint32 DFTCTRLREG1; /* 0x0090 */
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uint32 DFTCTRLREG2; /* 0x0094 */
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uint32 rsvd1; /* 0x0098 */
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uint32 rsvd2; /* 0x009C */
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uint32 GPREG1; /* 0x00A0 */
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uint32 BTRMSEL; /* 0x00A4 */
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uint32 IMPFASTS; /* 0x00A8 */
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uint32 IMPFTADD; /* 0x00AC */
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uint32 SSISR1; /* 0x00B0 */
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uint32 SSISR2; /* 0x00B4 */
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uint32 SSISR3; /* 0x00B8 */
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uint32 SSISR4; /* 0x00BC */
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uint32 RAMGCR; /* 0x00C0 */
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uint32 BMMCR1; /* 0x00C4 */
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uint32 BMMCR2; /* 0x00C8 */
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uint32 MMUGCR; /* 0x00CC */
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uint32 CLKCNTL; /* 0x00D0 */
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uint32 ECPCNTL; /* 0x00D4 */
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uint32 DSPGCR; /* 0x00D8 */
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uint32 DEVCR1; /* 0x00DC */
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uint32 SYSECR; /* 0x00E0 */
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uint32 SYSESR; /* 0x00E4 */
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uint32 SYSTASR; /* 0x00E8 */
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uint32 GBLSTAT; /* 0x00EC */
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uint32 DEV; /* 0x00F0 */
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uint32 SSIVEC; /* 0x00F4 */
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uint32 SSIF; /* 0x00F8 */
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uint32 SSIR1; /* 0x00FC */
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} systemBASE1_t;
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/** @def systemREG1
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* @brief System Register Frame 1 Pointer
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*
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* This pointer is used by the system driver to access the system frame 1 registers.
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*/
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#define systemREG1 ((systemBASE1_t *)0xFFFFFF00U)
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/** @def systemPORT
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* @brief ECLK GIO Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of System/Eclk
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* (use the GIO drivers to access the port pins).
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*/
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#define systemPORT ((gioPORT_t *)0xFFFFFF04U)
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* System Register Frame 2 Definition */
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/** @struct systemBase2
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* @brief System Register Frame 2 Definition
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*
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* This type is used to access the System 2 Registers.
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*/
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/** @typedef systemBASE2_t
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* @brief System Register Frame 2 Type Definition
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*
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* This type is used to access the System 2 Registers.
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*/
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typedef volatile struct systemBase2
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{
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uint32 PLLCTL3; /* 0x0000 */
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uint32 rsvd1; /* 0x0004 */
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uint32 STCCLKDIV; /* 0x0008 */
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uint32 rsvd2[6U]; /* 0x000C */
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uint32 ECPCNTRL0; /* 0x0024 */
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uint32 rsvd3[5U]; /* 0x0028 */
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uint32 CLK2CNTL; /* 0x003C */
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uint32 VCLKACON1; /* 0x0040 */
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uint32 rsvd4[11U]; /* 0x0044 */
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uint32 CLKSLIP; /* 0x0070 */
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uint32 rsvd5[30U]; /* 0x0074 */
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uint32 EFC_CTLEN; /* 0x00EC */
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uint32 DIEIDL_REG0; /* 0x00F0 */
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uint32 DIEIDH_REG1; /* 0x00F4 */
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uint32 DIEIDL_REG2; /* 0x00F8 */
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uint32 DIEIDH_REG3; /* 0x00FC */
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} systemBASE2_t;
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/** @def systemREG2
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* @brief System Register Frame 2 Pointer
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*
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* This pointer is used by the system driver to access the system frame 2 registers.
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*/
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#define systemREG2 ((systemBASE2_t *)0xFFFFE100U)
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#endif
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