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f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
61 lines
2.0 KiB
C
61 lines
2.0 KiB
C
/** @file reg_stc.h
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* @brief STC Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* .
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* which are relevant for the System driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_STC_H__
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#define __REG_STC_H__
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#include "sys_common.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Stc Register Frame Definition */
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/** @struct stcBase
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* @brief STC Base Register Definition
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*
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* This structure is used to access the STC module registers.
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*/
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/** @typedef stcBASE_t
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* @brief STC Register Frame Type Definition
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*
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* This type is used to access the STC Registers.
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*/
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typedef volatile struct stcBase
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{
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uint32 STCGCR0; /**< 0x0000: STC Control Register 0 */
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uint32 STCGCR1; /**< 0x0004: STC Control Register 1 */
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uint32 STCTPR; /**< 0x0008: STC Self-Test Run Timeout Counter Preload Register */
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uint32 STCCADDR; /**< 0x000C: STC Self-Test Current ROM Address Register */
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uint32 STCCICR; /**< 0x0010: STC Self-Test Current Interval Count Register */
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uint32 STCGSTAT; /**< 0x0014: STC Self-Test Global Status Register */
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uint32 STCFSTAT; /**< 0x0018: STC Self-Test Fail Status Register */
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uint32 CPU1_CURMISR3; /**< 0x001C: STC CPU1 Current MISR Register */
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uint32 CPU1_CURMISR2; /**< 0x0020: STC CPU1 Current MISR Register */
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uint32 CPU1_CURMISR1; /**< 0x0024: STC CPU1 Current MISR Register */
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uint32 CPU1_CURMISR0; /**< 0x0028: STC CPU1 Current MISR Register */
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uint32 CPU2_CURMISR3; /**< 0x002C: STC CPU1 Current MISR Register */
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uint32 CPU2_CURMISR2; /**< 0x0030: STC CPU1 Current MISR Register */
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uint32 CPU2_CURMISR1; /**< 0x0034: STC CPU1 Current MISR Register */
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uint32 CPU2_CURMISR0; /**< 0x0038: STC CPU1 Current MISR Register */
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uint32 STCSCSCR; /**< 0x003C: STC Signature Compare Self-Check Register */
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} stcBASE_t;
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#define stcREG ((stcBASE_t *)0xFFFFE600U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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