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f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
130 lines
4.4 KiB
C
130 lines
4.4 KiB
C
/** @file reg_pinmux.h
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* @brief PINMUX Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the PINMUX driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_PINMUX_H__
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#define __REG_PINMUX_H__
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#include "sys_common.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* IOMM Revision and Boot Register */
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#define REVISION_REG (*(volatile uint32 *)0xFFFFEA00U)
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#define ENDIAN_REG (*(volatile uint32 *)0xFFFFEA20U)
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/* IOMM Error and Fault Registers */
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/** @struct iommErrFault
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* @brief IOMM Error and Fault Register Definition
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*
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* This structure is used to access the IOMM Error and Fault registers.
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*/
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typedef volatile struct iommErrFault
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{
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uint32 ERR_RAW_STATUS_REG; /* Error Raw Status / Set Register */
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uint32 ERR_ENABLED_STATUS_REG; /* Error Enabled Status / Clear Register */
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uint32 ERR_ENABLE_REG; /* Error Signaling Enable Register */
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uint32 ERR_ENABLE_CLR_REG; /* Error Signaling Enable Clear Register */
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uint32 rsvd; /* Reserved */
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uint32 FAULT_ADDRESS_REG; /* Fault Address Register */
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uint32 FAULT_STATUS_REG; /* Fault Status Register */
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uint32 FAULT_CLEAR_REG; /* Fault Clear Register */
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} iommErrFault_t;
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/* Pinmux Register Frame Definition */
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/** @struct pinMuxKicker
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* @brief Pin Muxing Kicker Register Definition
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*
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* This structure is used to access the Pin Muxing Kicker registers.
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*/
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typedef volatile struct pinMuxKicker
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{
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uint32 KICKER0; /* kicker 0 register */
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uint32 KICKER1; /* kicker 1 register */
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} pinMuxKICKER_t;
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/** @struct pinMuxBase
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* @brief PINMUX Register Definition
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*
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* This structure is used to access the PINMUX module registers.
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*/
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/** @typedef pinMuxBASE_t
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* @brief PINMUX Register Frame Type Definition
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*
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* This type is used to access the PINMUX Registers.
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*/
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typedef volatile struct pinMuxBase
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{
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uint32 PINMMR0; /**< 0xEB10 Pin Mux 0 register*/
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uint32 PINMMR1; /**< 0xEB14 Pin Mux 1 register*/
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uint32 PINMMR2; /**< 0xEB18 Pin Mux 2 register*/
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uint32 PINMMR3; /**< 0xEB1C Pin Mux 3 register*/
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uint32 PINMMR4; /**< 0xEB20 Pin Mux 4 register*/
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uint32 PINMMR5; /**< 0xEB24 Pin Mux 5 register*/
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uint32 PINMMR6; /**< 0xEB28 Pin Mux 6 register*/
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uint32 PINMMR7; /**< 0xEB2C Pin Mux 7 register*/
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uint32 PINMMR8; /**< 0xEB30 Pin Mux 8 register*/
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uint32 PINMMR9; /**< 0xEB34 Pin Mux 9 register*/
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uint32 PINMMR10; /**< 0xEB38 Pin Mux 10 register*/
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uint32 PINMMR11; /**< 0xEB3C Pin Mux 11 register*/
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uint32 PINMMR12; /**< 0xEB40 Pin Mux 12 register*/
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uint32 PINMMR13; /**< 0xEB44 Pin Mux 13 register*/
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uint32 PINMMR14; /**< 0xEB48 Pin Mux 14 register*/
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uint32 PINMMR15; /**< 0xEB4C Pin Mux 15 register*/
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uint32 PINMMR16; /**< 0xEB50 Pin Mux 16 register*/
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uint32 PINMMR17; /**< 0xEB54 Pin Mux 17 register*/
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uint32 PINMMR18; /**< 0xEB58 Pin Mux 18 register*/
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uint32 PINMMR19; /**< 0xEB5C Pin Mux 19 register*/
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uint32 PINMMR20; /**< 0xEB60 Pin Mux 20 register*/
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uint32 PINMMR21; /**< 0xEB64 Pin Mux 21 register*/
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uint32 PINMMR22; /**< 0xEB68 Pin Mux 22 register*/
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uint32 PINMMR23; /**< 0xEB6C Pin Mux 23 register*/
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uint32 PINMMR24; /**< 0xEB70 Pin Mux 24 register*/
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uint32 PINMMR25; /**< 0xEB74 Pin Mux 25 register*/
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uint32 PINMMR26; /**< 0xEB78 Pin Mux 26 register*/
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uint32 PINMMR27; /**< 0xEB7C Pin Mux 27 register*/
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uint32 PINMMR28; /**< 0xEB80 Pin Mux 28 register*/
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uint32 PINMMR29; /**< 0xEB84 Pin Mux 29 register*/
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uint32 PINMMR30; /**< 0xEB88 Pin Mux 30 register*/
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}pinMuxBASE_t;
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/** @def iommErrFaultReg
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* @brief IOMM Error Fault Register Frame Pointer
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*
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* This pointer is used to control IOMM Error and Fault across the device.
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*/
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#define iommErrFaultReg ((iommErrFault_t *) 0xFFFFEAEOU)
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/** @def kickerReg
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* @brief Pin Muxing Kicker Register Frame Pointer
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*
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* This pointer is used to enable and disable muxing accross the device.
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*/
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#define kickerReg ((pinMuxKICKER_t *) 0xFFFFEA38U)
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/** @def pinMuxReg
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* @brief Pin Muxing Control Register Frame Pointer
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*
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* This pointer is used to set the muxing registers accross the device.
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*/
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#define pinMuxReg ((pinMuxBASE_t *) 0xFFFFEB10U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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