219 lines
5.7 KiB
ArmAsm
219 lines
5.7 KiB
ArmAsm
/*
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* Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020/03/26 hqfang First Nuclei RISC-V porting implementation
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*/
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#include "riscv_encoding.h"
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.section .text.entry
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.align 8
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/**
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* \brief Global interrupt disabled
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* \details
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* This function disable global interrupt.
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* \remarks
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* - All the interrupt requests will be ignored by CPU.
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*/
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.macro DISABLE_MIE
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csrc CSR_MSTATUS, MSTATUS_MIE
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.endm
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/**
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* \brief Macro for context save
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* \details
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* This macro save ABI defined caller saved registers in the stack.
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* \remarks
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* - This Macro could use to save context when you enter to interrupt
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* or exception
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*/
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/* Save caller registers */
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.macro SAVE_CONTEXT
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csrrw sp, CSR_MSCRATCHCSWL, sp
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/* Allocate stack space for context saving */
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#ifndef __riscv_32e
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addi sp, sp, -20*REGBYTES
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#else
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addi sp, sp, -14*REGBYTES
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#endif /* __riscv_32e */
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STORE x1, 0*REGBYTES(sp)
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STORE x4, 1*REGBYTES(sp)
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STORE x5, 2*REGBYTES(sp)
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STORE x6, 3*REGBYTES(sp)
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STORE x7, 4*REGBYTES(sp)
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STORE x10, 5*REGBYTES(sp)
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STORE x11, 6*REGBYTES(sp)
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STORE x12, 7*REGBYTES(sp)
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STORE x13, 8*REGBYTES(sp)
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STORE x14, 9*REGBYTES(sp)
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STORE x15, 10*REGBYTES(sp)
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#ifndef __riscv_32e
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STORE x16, 14*REGBYTES(sp)
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STORE x17, 15*REGBYTES(sp)
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STORE x28, 16*REGBYTES(sp)
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STORE x29, 17*REGBYTES(sp)
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STORE x30, 18*REGBYTES(sp)
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STORE x31, 19*REGBYTES(sp)
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#endif /* __riscv_32e */
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.endm
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/**
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* \brief Macro for restore caller registers
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* \details
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* This macro restore ABI defined caller saved registers from stack.
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* \remarks
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* - You could use this macro to restore context before you want return
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* from interrupt or exeception
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*/
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/* Restore caller registers */
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.macro RESTORE_CONTEXT
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LOAD x1, 0*REGBYTES(sp)
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LOAD x4, 1*REGBYTES(sp)
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LOAD x5, 2*REGBYTES(sp)
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LOAD x6, 3*REGBYTES(sp)
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LOAD x7, 4*REGBYTES(sp)
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LOAD x10, 5*REGBYTES(sp)
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LOAD x11, 6*REGBYTES(sp)
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LOAD x12, 7*REGBYTES(sp)
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LOAD x13, 8*REGBYTES(sp)
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LOAD x14, 9*REGBYTES(sp)
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LOAD x15, 10*REGBYTES(sp)
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#ifndef __riscv_32e
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LOAD x16, 14*REGBYTES(sp)
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LOAD x17, 15*REGBYTES(sp)
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LOAD x28, 16*REGBYTES(sp)
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LOAD x29, 17*REGBYTES(sp)
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LOAD x30, 18*REGBYTES(sp)
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LOAD x31, 19*REGBYTES(sp)
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/* De-allocate the stack space */
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addi sp, sp, 20*REGBYTES
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#else
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/* De-allocate the stack space */
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addi sp, sp, 14*REGBYTES
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#endif /* __riscv_32e */
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csrrw sp, CSR_MSCRATCHCSWL, sp
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.endm
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/**
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* \brief Macro for save necessary CSRs to stack
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* \details
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* This macro store MCAUSE, MEPC, MSUBM to stack.
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*/
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.macro SAVE_CSR_CONTEXT
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/* Store CSR mcause to stack using pushmcause */
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csrrwi x0, CSR_PUSHMCAUSE, 11
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/* Store CSR mepc to stack using pushmepc */
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csrrwi x0, CSR_PUSHMEPC, 12
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/* Store CSR msub to stack using pushmsub */
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csrrwi x0, CSR_PUSHMSUBM, 13
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.endm
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/**
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* \brief Macro for restore necessary CSRs from stack
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* \details
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* This macro restore MSUBM, MEPC, MCAUSE from stack.
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*/
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.macro RESTORE_CSR_CONTEXT
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LOAD x5, 13*REGBYTES(sp)
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csrw CSR_MSUBM, x5
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LOAD x5, 12*REGBYTES(sp)
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csrw CSR_MEPC, x5
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LOAD x5, 11*REGBYTES(sp)
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csrw CSR_MCAUSE, x5
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.endm
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/**
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* \brief Exception/NMI Entry
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* \details
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* This function provide common entry functions for exception/nmi.
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* \remarks
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* This function provide a default exception/nmi entry.
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* ABI defined caller save register and some CSR registers
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* to be saved before enter interrupt handler and be restored before return.
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*/
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.section .text.trap
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/* In CLIC mode, the exeception entry must be 64bytes aligned */
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.align 6
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.global exc_entry
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exc_entry:
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/* Save the caller saving registers (context) */
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SAVE_CONTEXT
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/* Save the necessary CSR registers */
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SAVE_CSR_CONTEXT
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/*
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* Set the exception handler function arguments
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* argument 1: mcause value
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* argument 2: current stack point(SP) value
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*/
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csrr a0, mcause
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mv a1, sp
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/*
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* TODO: Call the exception handler function
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* By default, the function template is provided in
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* system_Device.c, you can adjust it as you want
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*/
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call core_exception_handler
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/* Restore the necessary CSR registers */
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RESTORE_CSR_CONTEXT
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/* Restore the caller saving registers (context) */
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RESTORE_CONTEXT
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/* Return to regular code */
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mret
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/**
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* \brief Non-Vector Interrupt Entry
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* \details
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* This function provide common entry functions for handling
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* non-vector interrupts
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* \remarks
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* This function provide a default non-vector interrupt entry.
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* ABI defined caller save register and some CSR registers need
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* to be saved before enter interrupt handler and be restored before return.
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*/
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.section .text.irq
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/* In CLIC mode, the interrupt entry must be 4bytes aligned */
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.align 2
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.global irq_entry
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/* This label will be set to MTVT2 register */
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irq_entry:
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/* Save the caller saving registers (context) */
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SAVE_CONTEXT
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/* Save the necessary CSR registers */
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SAVE_CSR_CONTEXT
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/* This special CSR read/write operation, which is actually
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* claim the CLIC to find its pending highest ID, if the ID
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* is not 0, then automatically enable the mstatus.MIE, and
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* jump to its vector-entry-label, and update the link register
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*/
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csrrw ra, CSR_JALMNXTI, ra
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/* Critical section with interrupts disabled */
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DISABLE_MIE
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/* Restore the necessary CSR registers */
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RESTORE_CSR_CONTEXT
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/* Restore the caller saving registers (context) */
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RESTORE_CONTEXT
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/* Return to regular code */
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mret
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/* Default Handler for Exceptions / Interrupts */
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.global default_intexc_handler
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Undef_Handler:
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default_intexc_handler:
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1:
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j 1b
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