260 lines
6.6 KiB
C
260 lines
6.6 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-19 Nations first version
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*/
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#include "board.h"
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#include <sys/time.h>
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#include <rtdevice.h>
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#ifdef BSP_USING_RTC
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uint32_t SynchPrediv, AsynchPrediv;
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static rt_err_t n32_rtc_get_timeval(struct timeval *tv)
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{
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struct tm tm_new = {0};
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RTC_DateType RTC_DateStructure;
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RTC_TimeType RTC_TimeStructure;
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RTC_GetTime(RTC_FORMAT_BIN, &RTC_TimeStructure);
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RTC_GetDate(RTC_FORMAT_BIN, &RTC_DateStructure);
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tm_new.tm_sec = RTC_TimeStructure.Seconds;
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tm_new.tm_min = RTC_TimeStructure.Minutes;
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tm_new.tm_hour = RTC_TimeStructure.Hours;
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tm_new.tm_wday = RTC_DateStructure.WeekDay;
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tm_new.tm_mday = RTC_DateStructure.Date;
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tm_new.tm_mon = RTC_DateStructure.Month - 1;
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tm_new.tm_year = RTC_DateStructure.Year + 100;
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tv->tv_sec = timegm(&tm_new);
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return RT_EOK;
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}
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static rt_err_t set_rtc_time_stamp(time_t time_stamp)
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{
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struct tm time = {0};
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RTC_DateType RTC_DateStructure={0};
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RTC_TimeType RTC_TimeStructure={0};
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gmtime_r(&time_stamp, &time);
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if (time.tm_year < 100)
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{
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return -RT_ERROR;
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}
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RTC_TimeStructure.Seconds = time.tm_sec ;
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RTC_TimeStructure.Minutes = time.tm_min ;
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RTC_TimeStructure.Hours = time.tm_hour;
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RTC_DateStructure.Date = time.tm_mday;
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RTC_DateStructure.Month = time.tm_mon + 1 ;
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RTC_DateStructure.Year = time.tm_year - 100;
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RTC_DateStructure.WeekDay = time.tm_wday + 1;
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/* Configure the RTC date register */
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if (RTC_SetDate(RTC_FORMAT_BIN, &RTC_DateStructure) != SUCCESS)
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{
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return -RT_ERROR;
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}
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/* Configure the RTC time register */
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if (RTC_ConfigTime(RTC_FORMAT_BIN, &RTC_TimeStructure) != SUCCESS)
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{
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return -RT_ERROR;
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}
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rt_kprintf("set rtc time.\n");
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return RT_EOK;
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}
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static rt_err_t rt_rtc_config(void)
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{
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RTC_InitType RTC_InitStructure;
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/* Configure the RTC data register and RTC prescaler */
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RTC_InitStructure.RTC_AsynchPrediv = AsynchPrediv;
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RTC_InitStructure.RTC_SynchPrediv = SynchPrediv;
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RTC_InitStructure.RTC_HourFormat = RTC_24HOUR_FORMAT;
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/* Check on RTC init */
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if (RTC_Init(&RTC_InitStructure) != SUCCESS)
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{
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return -RT_ERROR;
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}
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return RT_EOK;
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}
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static rt_err_t n32_rtc_init(void)
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{
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/* Enable the PWR clock */
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#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
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RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR | RCC_APB1_PERIPH_BKP, ENABLE);
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RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
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#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
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RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR, ENABLE);
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RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
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#endif
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/* Allow access to RTC */
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PWR_BackupAccessEnable(ENABLE);
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#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
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/* Reset Backup */
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BKP_DeInit();
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#endif
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/* Disable RTC clock */
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RCC_EnableRtcClk(DISABLE);
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#ifdef BSP_RTC_USING_HSE
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/* Enable the HSE OSC */
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RCC_EnableLsi(DISABLE);
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RCC_ConfigHse(RCC_HSE_ENABLE);
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while (RCC_WaitHseStable() == ERROR)
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{
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}
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#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
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rt_kprintf("rtc clock source is set hse/128!\n");
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RCC_ConfigRtcClk(RCC_RTCCLK_SRC_HSE_DIV128);
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#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
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rt_kprintf("rtc clock source is set hse/32!\n");
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RCC_ConfigRtcClk(RCC_RTCCLK_SRC_HSE_DIV32);
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#endif
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#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
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SynchPrediv = 0x1E8; // 8M/128 = 62.5KHz
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AsynchPrediv = 0x7F; // value range: 0-7F
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#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
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SynchPrediv = 0x7A0; // 8M/32 = 250KHz
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AsynchPrediv = 0x7F; // value range: 0-7F
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#endif
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#endif /* BSP_RTC_USING_HSE */
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#ifdef BSP_RTC_USING_LSE
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rt_kprintf("rtc clock source is set lse!\n");
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/* Enable the LSE OSC32_IN PC14 */
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RCC_EnableLsi(DISABLE); // LSI is turned off here to ensure that only one clock is turned on
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#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
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RCC_ConfigLse(RCC_LSE_ENABLE);
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while (RCC_GetFlagStatus(RCC_FLAG_LSERD) == RESET)
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{
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}
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#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
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RCC_ConfigLse(RCC_LSE_ENABLE,0x28);
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while (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET)
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{
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}
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#endif
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RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSE);
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SynchPrediv = 0xFF; // 32.768KHz
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AsynchPrediv = 0x7F; // value range: 0-7F
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#endif /* BSP_RTC_USING_LSE */
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#ifdef BSP_RTC_USING_LSI
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rt_kprintf("rtc clock source is set lsi!\n");
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/* Enable the LSI OSC */
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RCC_EnableLsi(ENABLE);
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#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
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while (RCC_GetFlagStatus(RCC_FLAG_LSIRD) == RESET)
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{
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}
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#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
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while (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET)
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{
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}
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#endif
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RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSI);
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#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
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SynchPrediv = 0x136; // 39.64928KHz
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AsynchPrediv = 0x7F; // value range: 0-7F
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#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
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SynchPrediv = 0x14A; // 41828Hz
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AsynchPrediv = 0x7F; // value range: 0-7F
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#endif
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#endif /* BSP_RTC_USING_LSI */
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/* Enable the RTC Clock */
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RCC_EnableRtcClk(ENABLE);
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RTC_WaitForSynchro();
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if (rt_rtc_config() != RT_EOK)
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{
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rt_kprintf("rtc init failed.\n");
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return -RT_ERROR;
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}
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return RT_EOK;
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}
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static rt_err_t n32_rtc_get_secs(time_t *sec)
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{
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struct timeval tv;
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n32_rtc_get_timeval(&tv);
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*(time_t *) sec = tv.tv_sec;
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rt_kprintf("RTC: get rtc_time %d.\n", *sec);
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return RT_EOK;
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}
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static rt_err_t n32_rtc_set_secs(time_t *sec)
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{
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rt_err_t result = RT_EOK;
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if (set_rtc_time_stamp(*sec))
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{
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result = -RT_ERROR;
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}
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rt_kprintf("RTC: set rtc_time %d.\n", *sec);
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return result;
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}
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static const struct rt_rtc_ops n32_rtc_ops =
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{
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n32_rtc_init,
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n32_rtc_get_secs,
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n32_rtc_set_secs,
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RT_NULL,
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RT_NULL,
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n32_rtc_get_timeval,
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RT_NULL,
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};
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static rt_rtc_dev_t n32_rtc_dev;
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static int rt_hw_rtc_init(void)
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{
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rt_err_t result;
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n32_rtc_dev.ops = &n32_rtc_ops;
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result = rt_hw_rtc_register(&n32_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL);
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if (result != RT_EOK)
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{
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rt_kprintf("rtc register error code: %d.\n", result);
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return result;
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}
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else
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{
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rt_kprintf("rtc initialize success.\n");
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}
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return RT_EOK;
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}
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INIT_DEVICE_EXPORT(rt_hw_rtc_init);
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#endif /* BSP_USING_RTC */
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