65 lines
2.3 KiB
C
65 lines
2.3 KiB
C
/*
|
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*
|
|
* Change Logs:
|
|
* Date Author Notes
|
|
* 2019-02-16 jinsheng The first version for STM32F7xx
|
|
*/
|
|
|
|
#ifndef __SDRAM_PORT_H__
|
|
#define __SDRAM_PORT_H__
|
|
|
|
/* parameters for sdram peripheral */
|
|
/* Bank1 or Bank2 */
|
|
#define SDRAM_TARGET_BANK 1
|
|
/* stm32f7 Bank1:0XC0000000 Bank2:0XD0000000 */
|
|
#define SDRAM_BANK_ADDR ((uint32_t)0XC0000000)
|
|
/* data width: 8, 16, 32 */
|
|
#define SDRAM_DATA_WIDTH 16
|
|
/* column bit numbers: 8, 9, 10, 11 */
|
|
#define SDRAM_COLUMN_BITS 9
|
|
/* row bit numbers: 11, 12, 13 */
|
|
#define SDRAM_ROW_BITS 13
|
|
/* cas latency clock number: 1, 2, 3 */
|
|
#define SDRAM_CAS_LATENCY 3
|
|
/* read pipe delay: 0, 1, 2 */
|
|
#define SDRAM_RPIPE_DELAY 1
|
|
/* clock divid: 2, 3 */
|
|
#define SDCLOCK_PERIOD 2
|
|
/* refresh rate counter */
|
|
#define SDRAM_REFRESH_COUNT ((uint32_t)0x02AB)
|
|
#define SDRAM_SIZE ((uint32_t)0x1000000)
|
|
|
|
/* Timing configuration for MT48LC4M32B2B5-6A */
|
|
/* TMRD: 2 Clock cycles */
|
|
#define LOADTOACTIVEDELAY 2
|
|
/* TXSR: 7x11.90ns */
|
|
#define EXITSELFREFRESHDELAY 8
|
|
/* TRAS: 4x11.90ns */
|
|
#define SELFREFRESHTIME 6
|
|
/* TRC: 7x11.90ns */
|
|
#define ROWCYCLEDELAY 6
|
|
/* TWR: 2 Clock cycles */
|
|
#define WRITERECOVERYTIME 2
|
|
/* TRP: 2x11.90ns */
|
|
#define RPDELAY 2
|
|
/* TRCD: 2x11.90ns */
|
|
#define RCDDELAY 2
|
|
|
|
/* memory mode register */
|
|
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
|
|
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
|
|
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
|
|
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
|
|
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
|
|
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
|
|
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
|
|
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
|
|
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
|
|
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
|
|
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
|
|
|
|
#endif
|