552 lines
14 KiB
C
552 lines
14 KiB
C
#include <board.h>
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#include <rtthread.h>
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#include <netif/ethernetif.h>
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#include <lwipopts.h>
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#define MAX_ADDR_LEN 6
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#define SMC911X_EMAC_DEVICE(eth) (struct eth_device_smc911x*)(eth)
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#include "drv_smc911x.h"
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#define DRIVERNAME "EMAC"
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struct eth_device_smc911x
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{
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/* inherit from Ethernet device */
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struct eth_device parent;
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/* interface address info. */
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rt_uint8_t enetaddr[MAX_ADDR_LEN]; /* MAC address */
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uint32_t iobase;
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uint32_t irqno;
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};
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static struct eth_device_smc911x _emac;
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int udelay(int value)
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{
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return 0;
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}
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int mdelay(int value)
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{
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return 0;
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}
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#if defined (CONFIG_SMC911X_32_BIT)
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rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
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{
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return *(volatile uint32_t*)(dev->iobase + offset);
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}
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rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
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{
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*(volatile uint32_t*)(dev->iobase + offset) = val;
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}
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#elif defined (CONFIG_SMC911X_16_BIT)
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rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
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{
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volatile uint16_t *addr_16 = (uint16_t *)(dev->iobase + offset);
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return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
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}
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rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
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{
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*(volatile uint16_t *)(dev->iobase + offset) = (uint16_t)val;
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*(volatile uint16_t *)(dev->iobase + offset + 2) = (uint16_t)(val >> 16);
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}
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#else
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#error "SMC911X: undefined bus width"
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#endif /* CONFIG_SMC911X_16_BIT */
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struct chip_id
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{
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uint16_t id;
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char *name;
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};
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static const struct chip_id chip_ids[] =
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{
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{ CHIP_89218,"LAN89218" },
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{ CHIP_9115, "LAN9115" },
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{ CHIP_9116, "LAN9116" },
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{ CHIP_9117, "LAN9117" },
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{ CHIP_9118, "LAN9118" },
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{ CHIP_9211, "LAN9211" },
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{ CHIP_9215, "LAN9215" },
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{ CHIP_9216, "LAN9216" },
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{ CHIP_9217, "LAN9217" },
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{ CHIP_9218, "LAN9218" },
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{ CHIP_9220, "LAN9220" },
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{ CHIP_9221, "LAN9221" },
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{ 0, RT_NULL },
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};
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static uint32_t smc911x_get_mac_csr(struct eth_device_smc911x *dev, uint8_t reg)
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{
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while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
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smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
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while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
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return smc911x_reg_read(dev, MAC_CSR_DATA);
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}
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static void smc911x_set_mac_csr(struct eth_device_smc911x *dev, uint8_t reg, uint32_t data)
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{
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while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
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smc911x_reg_write(dev, MAC_CSR_DATA, data);
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smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
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while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
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}
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static int smc911x_detect_chip(struct eth_device_smc911x *dev)
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{
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unsigned long val, i;
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val = smc911x_reg_read(dev, BYTE_TEST);
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if (val == 0xffffffff)
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{
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/* Special case -- no chip present */
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return -1;
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}
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else if (val != 0x87654321)
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{
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rt_kprintf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
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return -1;
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}
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val = smc911x_reg_read(dev, ID_REV) >> 16;
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for (i = 0; chip_ids[i].id != 0; i++)
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{
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if (chip_ids[i].id == val) break;
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}
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if (!chip_ids[i].id)
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{
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rt_kprintf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
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return -1;
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}
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return 0;
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}
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static void smc911x_reset(struct eth_device_smc911x *dev)
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{
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int timeout;
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/*
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* Take out of PM setting first
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* Device is already wake up if PMT_CTRL_READY bit is set
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*/
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if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0)
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{
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/* Write to the bytetest will take out of powerdown */
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smc911x_reg_write(dev, BYTE_TEST, 0x0);
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timeout = 10;
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while (timeout-- && !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
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udelay(10);
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if (timeout < 0)
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{
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rt_kprintf(DRIVERNAME
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": timeout waiting for PM restore\n");
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return;
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}
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}
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/* Disable interrupts */
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smc911x_reg_write(dev, INT_EN, 0);
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smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
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timeout = 1000;
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while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
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udelay(10);
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if (timeout < 0)
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{
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rt_kprintf(DRIVERNAME ": reset timeout\n");
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return;
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}
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/* Reset the FIFO level and flow control settings */
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smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
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smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
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/* Set to LED outputs */
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smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
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}
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static void smc911x_handle_mac_address(struct eth_device_smc911x *dev)
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{
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unsigned long addrh, addrl;
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uint8_t *m = dev->enetaddr;
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addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
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addrh = m[4] | (m[5] << 8);
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smc911x_set_mac_csr(dev, ADDRL, addrl);
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smc911x_set_mac_csr(dev, ADDRH, addrh);
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}
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static int smc911x_eth_phy_read(struct eth_device_smc911x *dev,
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uint8_t phy, uint8_t reg, uint16_t *val)
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{
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while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) ;
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smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY);
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while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) ;
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*val = smc911x_get_mac_csr(dev, MII_DATA);
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return 0;
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}
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static int smc911x_eth_phy_write(struct eth_device_smc911x *dev,
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uint8_t phy, uint8_t reg, uint16_t val)
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{
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while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
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;
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smc911x_set_mac_csr(dev, MII_DATA, val);
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smc911x_set_mac_csr(dev, MII_ACC,
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phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
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while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
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;
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return 0;
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}
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static int smc911x_phy_reset(struct eth_device_smc911x *dev)
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{
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uint32_t reg;
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reg = smc911x_reg_read(dev, PMT_CTRL);
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reg &= ~0xfffff030;
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reg |= PMT_CTRL_PHY_RST;
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smc911x_reg_write(dev, PMT_CTRL, reg);
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mdelay(100);
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return 0;
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}
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static void smc911x_phy_configure(struct eth_device_smc911x *dev)
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{
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int timeout;
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uint16_t status;
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smc911x_phy_reset(dev);
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smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET);
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mdelay(1);
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smc911x_eth_phy_write(dev, 1, MII_ADVERTISE, 0x01e1);
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smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
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timeout = 5000;
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do
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{
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mdelay(1);
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if ((timeout--) == 0)
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goto err_out;
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if (smc911x_eth_phy_read(dev, 1, MII_BMSR, &status) != 0)
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goto err_out;
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}
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while (!(status & BMSR_LSTATUS));
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return;
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err_out:
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rt_kprintf(DRIVERNAME ": autonegotiation timed out\n");
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}
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static void smc911x_enable(struct eth_device_smc911x *dev)
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{
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/* Enable TX */
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smc911x_reg_write(dev, HW_CFG, 8 << 16 | HW_CFG_SF);
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smc911x_reg_write(dev, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
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smc911x_reg_write(dev, TX_CFG, TX_CFG_TX_ON);
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/* no padding to start of packets */
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smc911x_reg_write(dev, RX_CFG, 0);
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smc911x_set_mac_csr(dev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
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MAC_CR_HBDIS);
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}
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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/* wrapper for smc911x_eth_phy_read */
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static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
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int reg)
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{
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uint16_t val = 0;
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struct eth_device_smc911x *dev = eth_get_dev_by_name(bus->name);
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if (dev)
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{
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int retval = smc911x_eth_phy_read(dev, phy, reg, &val);
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if (retval < 0)
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return retval;
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return val;
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}
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return -ENODEV;
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}
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/* wrapper for smc911x_eth_phy_write */
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static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
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int reg, uint16_t val)
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{
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struct eth_device_smc911x *dev = eth_get_dev_by_name(bus->name);
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if (dev)
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return smc911x_eth_phy_write(dev, phy, reg, val);
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return -ENODEV;
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}
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#endif
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static void smc911x_isr(int vector, void *param)
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{
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uint32_t status;
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struct eth_device_smc911x *emac;
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emac = SMC911X_EMAC_DEVICE(param);
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status = smc911x_reg_read(emac, INT_STS);
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if (status & INT_STS_RSFL)
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{
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eth_device_ready(&emac->parent);
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}
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smc911x_reg_write(emac, INT_STS, status);
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return ;
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}
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static rt_err_t smc911x_emac_init(rt_device_t dev)
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{
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// uint32_t value;
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struct eth_device_smc911x *emac;
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emac = SMC911X_EMAC_DEVICE(dev);
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RT_ASSERT(emac != RT_NULL);
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smc911x_reset(emac);
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/* Configure the PHY, initialize the link state */
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smc911x_phy_configure(emac);
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smc911x_handle_mac_address(emac);
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/* Turn on Tx + Rx */
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smc911x_enable(emac);
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#if 1
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/* Interrupt on every received packet */
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smc911x_reg_write(emac, FIFO_INT, 0x01 << 8);
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smc911x_reg_write(emac, INT_EN, INT_EN_RDFL_EN | INT_EN_RSFL_EN);
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/* enable interrupt */
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smc911x_reg_write(emac, INT_CFG, INT_CFG_IRQ_EN | INT_CFG_IRQ_POL | INT_CFG_IRQ_TYPE);
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#else
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/* disable interrupt */
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smc911x_reg_write(emac, INT_EN, 0);
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value = smc911x_reg_read(emac, INT_CFG);
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value &= ~INT_CFG_IRQ_EN;
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smc911x_reg_write(emac, INT_CFG, value);
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#endif
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rt_hw_interrupt_install(emac->irqno, smc911x_isr, emac, "smc911x");
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rt_hw_interrupt_umask(emac->irqno);
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return RT_EOK;
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}
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static rt_err_t smc911x_emac_control(rt_device_t dev, int cmd, void *args)
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{
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struct eth_device_smc911x *emac;
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emac = SMC911X_EMAC_DEVICE(dev);
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RT_ASSERT(emac != RT_NULL);
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switch(cmd)
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{
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case NIOCTL_GADDR:
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/* get MAC address */
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if(args) rt_memcpy(args, emac->enetaddr, 6);
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else return -RT_ERROR;
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break;
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default :
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break;
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}
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return RT_EOK;
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}
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/* Ethernet device interface */
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/* transmit packet. */
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static uint8_t tx_buf[2048];
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rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf* p)
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{
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struct eth_device_smc911x *emac;
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uint32_t *data;
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uint32_t tmplen;
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uint32_t status;
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uint32_t length;
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emac = SMC911X_EMAC_DEVICE(dev);
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RT_ASSERT(emac != RT_NULL);
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/* copy pbuf to a whole ETH frame */
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pbuf_copy_partial(p, tx_buf, p->tot_len, 0);
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/* send it out */
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data = (uint32_t*)tx_buf;
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length = p->tot_len;
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smc911x_reg_write(emac, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length);
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smc911x_reg_write(emac, TX_DATA_FIFO, length);
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tmplen = (length + 3) / 4;
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while (tmplen--)
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{
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smc911x_reg_write(emac, TX_DATA_FIFO, *data++);
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}
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/* wait for transmission */
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while (!((smc911x_reg_read(emac, TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16));
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/* get status. Ignore 'no carrier' error, it has no meaning for
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* full duplex operation
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*/
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status = smc911x_reg_read(emac, TX_STATUS_FIFO) &
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(TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL |
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TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
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if (!status) return 0;
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rt_kprintf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
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status & TX_STS_LOC ? "TX_STS_LOC " : "",
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status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "",
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status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "",
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status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "",
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status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : "");
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return -RT_EIO;
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}
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/* reception packet. */
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struct pbuf *smc911x_emac_rx(rt_device_t dev)
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{
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struct pbuf* p = RT_NULL;
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struct eth_device_smc911x *emac;
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emac = SMC911X_EMAC_DEVICE(dev);
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RT_ASSERT(emac != RT_NULL);
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/* take the emac buffer to the pbuf */
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if ((smc911x_reg_read(emac, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16)
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{
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uint32_t status;
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uint32_t pktlen, tmplen;
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status = smc911x_reg_read(emac, RX_STATUS_FIFO);
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/* get frame length */
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pktlen = (status & RX_STS_PKT_LEN) >> 16;
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smc911x_reg_write(emac, RX_CFG, 0);
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tmplen = (pktlen + 3) / 4;
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/* allocate pbuf */
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p = pbuf_alloc(PBUF_LINK, tmplen * 4, PBUF_RAM);
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if (p)
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{
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uint32_t *data = (uint32_t *)p->payload;
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while (tmplen--)
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{
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*data++ = smc911x_reg_read(emac, RX_DATA_FIFO);
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}
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}
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if (status & RX_STS_ES)
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{
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rt_kprintf(DRIVERNAME ": dropped bad packet. Status: 0x%08x\n", status);
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}
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}
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return p;
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}
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int smc911x_emac_hw_init(void)
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{
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_emac.iobase = VEXPRESS_ETH_BASE;
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_emac.irqno = IRQ_VEXPRESS_A9_ETH;
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if (smc911x_detect_chip(&_emac))
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{
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rt_kprintf("no smc911x network interface found!\n");
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return -1;
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}
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/* set INT CFG */
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smc911x_reg_write(&_emac, INT_CFG, INT_CFG_IRQ_POL | INT_CFG_IRQ_TYPE);
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|
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/* test MAC address */
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_emac.enetaddr[0] = 0x52;
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_emac.enetaddr[1] = 0x54;
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_emac.enetaddr[2] = 0x00;
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_emac.enetaddr[3] = 0x11;
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_emac.enetaddr[4] = 0x22;
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_emac.enetaddr[5] = 0x33;
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|
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_emac.parent.parent.init = smc911x_emac_init;
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_emac.parent.parent.open = RT_NULL;
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_emac.parent.parent.close = RT_NULL;
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_emac.parent.parent.read = RT_NULL;
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_emac.parent.parent.write = RT_NULL;
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_emac.parent.parent.control = smc911x_emac_control;
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_emac.parent.parent.user_data = RT_NULL;
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_emac.parent.eth_rx = smc911x_emac_rx;
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_emac.parent.eth_tx = smc911x_emac_tx;
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|
|
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/* register ETH device */
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eth_device_init(&(_emac.parent), "e0");
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|
|
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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{
|
|
int retval;
|
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struct mii_dev *mdiodev = mdio_alloc();
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|
if (!mdiodev)
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return -ENOMEM;
|
|
strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
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mdiodev->read = smc911x_miiphy_read;
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mdiodev->write = smc911x_miiphy_write;
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|
|
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retval = mdio_register(mdiodev);
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if (retval < 0)
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return retval;
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}
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#endif
|
|
|
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eth_device_linkchange(&_emac.parent, RT_TRUE);
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return 0;
|
|
}
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|
INIT_APP_EXPORT(smc911x_emac_hw_init);
|
|
|
|
#include <finsh.h>
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|
int emac(int argc, char** argv)
|
|
{
|
|
rt_hw_interrupt_umask(_emac.irqno);
|
|
|
|
return 0;
|
|
}
|
|
MSH_CMD_EXPORT(emac, emac dump);
|