491 lines
15 KiB
C
491 lines
15 KiB
C
/*
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* Copyright (c) 2023 HPMicro
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include "board.h"
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#include "hpm_uart_drv.h"
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#include "hpm_gptmr_drv.h"
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#include "hpm_gpio_drv.h"
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#include "hpm_usb_drv.h"
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#include "hpm_clock_drv.h"
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#include "hpm_pllctlv2_drv.h"
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#include "hpm_i2c_drv.h"
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#include "hpm_pcfg_drv.h"
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static board_timer_cb timer_cb;
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/**
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* @brief FLASH configuration option definitions:
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* option[0]:
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* [31:16] 0xfcf9 - FLASH configuration option tag
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* [15:4] 0 - Reserved
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* [3:0] option words (exclude option[0])
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* option[1]:
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* [31:28] Flash probe type
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* 0 - SFDP SDR / 1 - SFDP DDR
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* 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
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* 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
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* 6 - OctaBus DDR (SPI -> OPI DDR)
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* 8 - Xccela DDR (SPI -> OPI DDR)
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* 10 - EcoXiP DDR (SPI -> OPI DDR)
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* [27:24] Command Pads after Power-on Reset
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* 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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* [23:20] Command Pads after Configuring FLASH
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* 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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* [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
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* 0 - Not needed
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* 1 - QE bit is at bit 6 in Status Register 1
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* 2 - QE bit is at bit1 in Status Register 2
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* 3 - QE bit is at bit7 in Status Register 2
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* 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
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* [15:8] Dummy cycles
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* 0 - Auto-probed / detected / default value
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* Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
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* [7:4] Misc.
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* 0 - Not used
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* 1 - SPI mode
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* 2 - Internal loopback
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* 3 - External DQS
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* [3:0] Frequency option
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* 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
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*
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* option[2] (Effective only if the bit[3:0] in option[0] > 1)
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* [31:20] Reserved
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* [19:16] IO voltage
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* 0 - 3V / 1 - 1.8V
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* [15:12] Pin group
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* 0 - 1st group / 1 - 2nd group
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* [11:8] Connection selection
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* 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
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* [7:0] Drive Strength
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* 0 - Default value
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* option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
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* JESD216)
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* [31:16] reserved
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* [15:12] Sector Erase Command Option, not required here
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* [11:8] Sector Size Option, not required here
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* [7:0] Flash Size Option
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* 0 - 4MB / 1 - 8MB / 2 - 16MB
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*/
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#if defined(FLASH_XIP) && FLASH_XIP
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__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90002, 0x00000006, 0x1000, 0x0};
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#endif
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#if defined(FLASH_UF2) && FLASH_UF2
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ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
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#endif
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void board_init_console(void)
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{
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#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
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#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
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console_config_t cfg;
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/* uart needs to configure pin function before enabling clock, otherwise the level change of
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* uart rx pin when configuring pin function will cause a wrong data to be received.
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* And a uart rx dma request will be generated by default uart fifo dma trigger level.
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*/
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init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE);
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/* Configure the UART clock to 24MHz */
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clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U);
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clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0);
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cfg.type = BOARD_CONSOLE_TYPE;
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cfg.base = (uint32_t)BOARD_CONSOLE_UART_BASE;
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cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME);
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cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE;
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if (status_success != console_init(&cfg)) {
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/* failed to initialize debug console */
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while (1) {
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}
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}
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#else
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while (1)
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;
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#endif
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#endif
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}
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void board_print_banner(void)
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{
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const uint8_t banner[] = "\n"
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"----------------------------------------------------------------------\n"
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"$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n"
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"$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n"
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"$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n"
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"$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n"
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"$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n"
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"$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n"
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"$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n"
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"\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n"
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"----------------------------------------------------------------------\n";
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#ifdef SDK_VERSION_STRING
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printf("hpm_sdk: %s\n", SDK_VERSION_STRING);
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#endif
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printf("%s", banner);
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}
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void board_print_clock_freq(void)
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{
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printf("==============================\n");
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printf(" %s clock summary\n", BOARD_NAME);
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printf("==============================\n");
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printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0));
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printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb));
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printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0));
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printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0));
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printf("==============================\n");
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}
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void board_init(void)
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{
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init_xtal_pins();
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init_py_pins_as_pgpio();
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board_init_usb_dp_dm_pins();
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board_init_clock();
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board_init_console();
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board_init_pmp();
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#if BOARD_SHOW_CLOCK
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board_print_clock_freq();
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#endif
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#if BOARD_SHOW_BANNER
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board_print_banner();
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#endif
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}
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void board_init_usb_dp_dm_pins(void)
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{
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/* Disconnect usb dp/dm pins pull down 45ohm resistance */
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while (sysctl_resource_any_is_busy(HPM_SYSCTL)) {
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;
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}
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if (pllctlv2_xtal_is_stable(HPM_PLLCTLV2) && pllctlv2_xtal_is_enabled(HPM_PLLCTLV2)) {
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if (clock_check_in_group(clock_usb0, 0)) {
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usb_phy_disable_dp_dm_pulldown(HPM_USB0);
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} else {
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clock_add_to_group(clock_usb0, 0);
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usb_phy_disable_dp_dm_pulldown(HPM_USB0);
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clock_remove_from_group(clock_usb0, 0);
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}
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} else {
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uint8_t tmp;
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tmp = sysctl_resource_target_get_mode(HPM_SYSCTL, sysctl_resource_xtal);
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sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03);
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clock_add_to_group(clock_usb0, 0);
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usb_phy_disable_dp_dm_pulldown(HPM_USB0);
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clock_remove_from_group(clock_usb0, 0);
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while (sysctl_resource_target_is_busy(HPM_SYSCTL, sysctl_resource_usb0)) {
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;
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}
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sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, tmp);
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}
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}
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void board_init_clock(void)
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{
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uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
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if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
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/* Configure the External OSC ramp-up time: ~9ms */
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pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U);
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/* Select clock setting preset1 */
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sysctl_clock_set_preset(HPM_SYSCTL, 2);
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}
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/* group0[0] */
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clock_add_to_group(clock_cpu0, 0);
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clock_add_to_group(clock_ahb, 0);
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clock_add_to_group(clock_lmm0, 0);
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clock_add_to_group(clock_mchtmr0, 0);
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clock_add_to_group(clock_rom, 0);
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clock_add_to_group(clock_gptmr0, 0);
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clock_add_to_group(clock_gptmr1, 0);
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clock_add_to_group(clock_i2c2, 0);
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clock_add_to_group(clock_spi1, 0);
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clock_add_to_group(clock_uart0, 0);
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clock_add_to_group(clock_uart3, 0);
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clock_add_to_group(clock_watchdog0, 0);
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clock_add_to_group(clock_watchdog1, 0);
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clock_add_to_group(clock_mbx0, 0);
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clock_add_to_group(clock_tsns, 0);
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clock_add_to_group(clock_crc0, 0);
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clock_add_to_group(clock_adc0, 0);
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clock_add_to_group(clock_acmp, 0);
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clock_add_to_group(clock_kman, 0);
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clock_add_to_group(clock_gpio, 0);
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clock_add_to_group(clock_hdma, 0);
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clock_add_to_group(clock_xpi0, 0);
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clock_add_to_group(clock_usb0, 0);
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/* Connect Group0 to CPU0 */
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clock_connect_group_to_cpu(0, 0);
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/* Bump up DCDC voltage to 1175mv */
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pcfg_dcdc_set_voltage(HPM_PCFG, 1175);
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/* Configure CPU to 360MHz, AXI/AHB to 120MHz */
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sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll0_clk0, 2, 3);
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/* Configure PLL0 Post Divider */
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pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0); /* PLL0CLK0: 720MHz */
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pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 1, 3); /* PLL0CLK1: 450MHz */
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pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 2, 7); /* PLL0CLK2: 300MHz */
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/* Configure PLL0 Frequency to 720MHz */
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pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, 720000000);
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clock_update_core_clock();
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/* Configure mchtmr to 24MHz */
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clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
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}
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uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
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{
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uint32_t freq = 0;
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clock_name_t gptmr_clock =0;
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uint32_t HPM_GPTMR = (uint32_t)ptr;
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bool gptmr_valid = true;
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switch(HPM_GPTMR){
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case HPM_GPTMR0_BASE:
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gptmr_clock = clock_gptmr0;
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break;
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case HPM_GPTMR1_BASE:
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gptmr_clock = clock_gptmr1;
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break;
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default:
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gptmr_valid = false;
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}
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if(gptmr_valid)
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{
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clock_add_to_group(gptmr_clock, 0);
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clock_set_source_divider(gptmr_clock, clk_src_pll1_clk1, 4);
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freq = clock_get_frequency(gptmr_clock);
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}
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return freq;
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}
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void board_delay_us(uint32_t us)
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{
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clock_cpu_delay_us(us);
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}
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void board_delay_ms(uint32_t ms)
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{
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clock_cpu_delay_ms(ms);
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}
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void board_timer_create(uint32_t ms, board_timer_cb cb)
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{
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uint32_t gptmr_freq;
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gptmr_channel_config_t config;
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timer_cb = cb;
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gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);
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clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
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gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);
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config.reload = gptmr_freq / 1000 * ms;
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gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
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gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
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intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);
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gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
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}
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void board_init_gpio_pins(void)
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{
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init_gpio_pins();
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gpio_set_pin_input(BOARD_APP_GPIO_CTRL, BOARD_APP_GPIO_INDEX, BOARD_APP_GPIO_PIN);
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}
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void board_init_led_pins(void)
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{
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init_led_pins_as_gpio();
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gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level());
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}
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void board_init_usb_pins(void)
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{
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init_usb_pins();
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usb_hcd_set_power_ctrl_polarity(BOARD_USB, true);
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/* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */
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board_delay_ms(100);
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/* As QFN32, QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */
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usb_phy_using_internal_vbus(BOARD_USB);
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}
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void board_led_write(uint8_t state)
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{
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gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
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}
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void board_led_toggle(void)
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{
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gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
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}
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void board_init_uart(UART_Type *ptr)
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{
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/* configure uart's pin before opening uart's clock */
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init_uart_pins(ptr);
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board_init_uart_clock(ptr);
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}
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void board_ungate_mchtmr_at_lp_mode(void)
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{
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/* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */
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sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock);
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}
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uint32_t board_init_spi_clock(SPI_Type *ptr)
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{
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if (ptr == HPM_SPI1) {
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clock_add_to_group(clock_spi1, 0);
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return clock_get_frequency(clock_spi1);
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}
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return 0;
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}
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void board_init_spi_pins(SPI_Type *ptr)
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{
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init_spi_pins(ptr);
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}
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void board_write_spi_cs(uint32_t pin, uint8_t state)
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{
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gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state);
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}
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void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
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{
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init_spi_pins_with_gpio_as_cs(ptr);
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gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN),
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GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
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}
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void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
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{
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(void) usb_index;
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(void) level;
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}
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uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
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{
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uint32_t freq = 0;
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if (ptr == HPM_ADC0) {
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if (clk_src_ahb) {
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/* Configure the ADC clock from AHB (@200MHz by default)*/
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clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
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} else {
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/* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
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clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
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clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U);
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}
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freq = clock_get_frequency(clock_adc0);
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}
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return freq;
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}
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void board_init_adc16_pins(void)
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{
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init_adc_pins();
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}
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void board_disable_output_rgb_led(uint8_t color)
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{
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(void) color;
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}
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void board_enable_output_rgb_led(uint8_t color)
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{
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(void) color;
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}
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uint8_t board_get_led_gpio_off_level(void)
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{
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return BOARD_LED_OFF_LEVEL;
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}
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void board_init_pmp(void)
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{
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}
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uint32_t board_init_uart_clock(UART_Type *ptr)
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{
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uint32_t freq = 0U;
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if (ptr == HPM_UART0) {
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clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
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clock_add_to_group(clock_uart0, 0);
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freq = clock_get_frequency(clock_uart0);
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} else if (ptr == HPM_UART2) {
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clock_set_source_divider(clock_uart2, clk_src_pll0_clk2, 6);
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clock_add_to_group(clock_uart2, 0);
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freq = clock_get_frequency(clock_uart2);
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} else if (ptr == HPM_UART3) {
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clock_set_source_divider(clock_uart3, clk_src_pll0_clk2, 6); /* 50MHz */
|
|
clock_add_to_group(clock_uart3, 0);
|
|
freq = clock_get_frequency(clock_uart3);
|
|
}
|
|
|
|
return freq;
|
|
}
|
|
|
|
void board_i2c_bus_clear(I2C_Type *ptr)
|
|
{
|
|
if (i2c_get_line_scl_status(ptr) == false) {
|
|
printf("CLK is low, please power cycle the board\n");
|
|
while (1) {
|
|
}
|
|
}
|
|
if (i2c_get_line_sda_status(ptr) == false) {
|
|
printf("SDA is low, try to issue I2C bus clear\n");
|
|
} else {
|
|
printf("I2C bus is ready\n");
|
|
return;
|
|
}
|
|
i2s_gen_reset_signal(ptr, 9);
|
|
board_delay_ms(100);
|
|
printf("I2C bus is cleared\n");
|
|
}
|
|
|
|
void board_init_i2c(I2C_Type *ptr)
|
|
{
|
|
i2c_config_t config;
|
|
hpm_stat_t stat;
|
|
uint32_t freq;
|
|
if (ptr == NULL) {
|
|
return;
|
|
}
|
|
init_i2c_pins(ptr);
|
|
board_i2c_bus_clear(ptr);
|
|
|
|
clock_add_to_group(clock_i2c2, 0);
|
|
/* Configure the I2C clock to 24MHz */
|
|
clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U);
|
|
|
|
config.i2c_mode = i2c_mode_normal;
|
|
config.is_10bit_addressing = false;
|
|
freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME);
|
|
stat = i2c_init_master(ptr, freq, &config);
|
|
if (stat != status_success) {
|
|
printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr);
|
|
while (1) {
|
|
}
|
|
}
|
|
|
|
}
|
|
|