Grissiom f51bce3fed add rm48x50 bsp and libcpu ... We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.		2013-05-24 22:55:13 +08:00
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rtdebug.h	re-format the coding style, convert the tab to 4 spaces and make sure the line length is not longer than 80 in rtdebug.h	2012-09-05 06:52:35 +00:00
rtdef.h	add rm48x50 bsp and libcpu	2013-05-24 22:55:13 +08:00
rthw.h	code cleanup for interrupt description	2013-03-26 08:52:33 +08:00
rtm.h	app module support for simlator, first version	2013-02-27 00:37:57 +08:00
rtservice.h	add __RT_SERVICE_H__ definition	2012-10-13 03:26:25 +00:00
rtthread.h	add rm48x50 bsp and libcpu	2013-05-24 22:55:13 +08:00