rt-thread-official/bsp/pic32ethernet/board.c

64 lines
2.6 KiB
C

/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-05-23 aozima first implementation for PIC32.
*/
// Adds support for PIC32 Peripheral library functions and macros
#include <plib.h>
// Configuration Bits
#pragma config FNOSC = PRIPLL // Oscillator Selection
#pragma config FPLLIDIV = DIV_2 // PLL Input Divider (PIC32 Starter Kit: use divide by 2 only)
#pragma config FPLLMUL = MUL_20 // PLL Multiplier
#pragma config FPLLODIV = DIV_1 // PLL Output Divider
#pragma config FPBDIV = DIV_1 // Peripheral Clock divisor
#pragma config FWDTEN = OFF // Watchdog Timer
#pragma config WDTPS = PS1 // Watchdog Timer Postscale
#pragma config FCKSM = CSDCMD // Clock Switching & Fail Safe Clock Monitor
#pragma config OSCIOFNC = OFF // CLKO Enable
#pragma config POSCMOD = XT // Primary Oscillator
#pragma config IESO = OFF // Internal/External Switch-over
#pragma config FSOSCEN = OFF // Secondary Oscillator Enable
#pragma config CP = OFF // Code Protect
#pragma config BWP = OFF // Boot Flash Write Protect
#pragma config PWP = OFF // Program Flash Write Protect
#pragma config ICESEL = ICS_PGx2 // ICE/ICD Comm Channel Select
#pragma config DEBUG = OFF // Debugger Disabled for Starter Kit
// The following is used by the main application
#define SYS_FREQ (80000000)
static void rt_hw_show_info(void)
{
rt_kprintf("\r\n\r\n---------- board info ----------\r\n");
rt_kprintf("DEVICE_FAMILY: PIC32\r\n");
rt_kprintf("CPU_ARCHITECTURE: MIPS\r\n");
rt_kprintf("CPU_FREQ: %uMHz\r\n",SYS_FREQ/1000000UL);
}
/**
* This function will initial FM3 Easy Kit board.
*/
void rt_hw_board_init()
{
// Configure the device for maximum performance, but do not change the PBDIV clock divisor.
// Given the options, this function will change the program Flash wait states,
// RAM wait state and enable prefetch cache, but will not change the PBDIV.
// The PBDIV value is already set via the pragma FPBDIV option above.
SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE);
rt_hw_console_init();
rt_hw_show_info();
}