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https://github.com/RT-Thread/rt-thread.git
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2168ed8e7d
PCI/PCIe have better performance and more devices support, such as NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by IOMMU that the virtualiztion and userspace driver will more safety. PCI/PCIe device could hot plugging, no design modifications SoC required, PCI/PCIe on Embedded SoC is popular now. We make a simple framework to support them. Feature Lists: 1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC. 2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC. 3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework. 4.Endpoint: a simple EP framework for PCI FPGA or NTB function. 5.OFW: we only support work on OFW SoC, ACPI support in the future maybe. Host controller: 1. Common PCI host controller on ECAM. 2. Generic PCI host controller on ECAM. Signed-off-by: GuEe-GUI <2991707448@qq.com>
122 lines
3.3 KiB
C
122 lines
3.3 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-24 GuEe-GUI first version
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*/
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#include <drivers/pci.h>
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#include <drivers/core/power_domain.h>
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#define DBG_TAG "pci.pme"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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/*
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* Power Management Capability Register:
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*
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* 31 27 26 25 24 22 21 20 19 18 16 15 8 7 0
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* +---------+---+---+--------+---+---+---+------+-----------+----------------+
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* | | | | | | | | | | Capabilitiy ID |
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* +---------+---+---+--------+---+---+---+------+-----------+----------------+
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* ^ ^ ^ ^ ^ ^ ^ ^ ^
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* | | | | | | | | |
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* | | | | | | | | +---- Next Capabilitiy Pointer
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* | | | | | | | +------------- Version
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* | | | | | | +------------------- PME Clock
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* | | | | | +----------------------- Immediate Readiness on Return to D0
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* | | | | +--------------------------- Device Specifiic Initializtion
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* | | | +--------------------------------- Aux Current
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* | | +---------------------------------------- D1 Support
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* | +-------------------------------------------- D2 Support
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* +--------------------------------------------------- PME Support
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*/
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void rt_pci_pme_init(struct rt_pci_device *pdev)
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{
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rt_uint16_t pmc;
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if (!pdev || !(pdev->pme_cap = rt_pci_find_capability(pdev, PCIY_PMG)))
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{
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return;
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}
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rt_pci_read_config_u16(pdev, pdev->pme_cap + PCIR_POWER_CAP, &pmc);
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if ((pmc & PCIM_PCAP_SPEC) > 3)
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{
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LOG_E("%s: Unsupported PME CAP regs spec %u",
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rt_dm_dev_get_name(&pdev->parent), pmc & PCIM_PCAP_SPEC);
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return;
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}
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pmc &= PCIM_PCAP_PMEMASK;
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if (pmc)
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{
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pdev->pme_support = RT_FIELD_GET(PCIM_PCAP_PMEMASK, pmc);
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rt_pci_pme_active(pdev, RT_FALSE);
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}
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}
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rt_err_t rt_pci_enable_wake(struct rt_pci_device *pdev,
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enum rt_pci_power state, rt_bool_t enable)
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{
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if (!pdev || state >= RT_PCI_PME_MAX)
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{
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return -RT_EINVAL;
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}
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if (enable)
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{
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if (rt_pci_pme_capable(pdev, state) ||
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rt_pci_pme_capable(pdev, RT_PCI_D3COLD))
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{
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rt_pci_pme_active(pdev, RT_EOK);
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}
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}
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else
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{
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rt_pci_pme_active(pdev, RT_FALSE);
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}
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return RT_EOK;
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}
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static void pci_pme_active(struct rt_pci_device *pdev, rt_bool_t enable)
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{
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rt_uint16_t pmcsr;
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if (!pdev->pme_support)
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{
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return;
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}
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rt_pci_read_config_u16(pdev, pdev->pme_cap + PCIR_POWER_STATUS, &pmcsr);
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/* Clear PME_Status by writing 1 to it and enable PME# */
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pmcsr |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
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if (!enable)
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{
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pmcsr &= ~PCIM_PSTAT_PMEENABLE;
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}
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rt_pci_write_config_u16(pdev, pdev->pme_cap + PCIR_POWER_STATUS, pmcsr);
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}
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void rt_pci_pme_active(struct rt_pci_device *pdev, rt_bool_t enable)
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{
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if (!pdev)
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{
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return;
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}
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pci_pme_active(pdev, enable);
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rt_dm_power_domain_attach(&pdev->parent, enable);
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}
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