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10ec208306
1. Upgrade EFM32 driver libraries (CMSIS and efm32lib): version 2.3.0 -> 2.3.2 2. Upgrade EFM32GG_DK3750 development kit driver library: version 1.2.1 -> 1.2.2 3. Upgrade EFM32_Gxxx_DK development kit driver library: version 1.7.2 -> 1.7.3 4. Add LCD driver (SSD2119) and DEMO 5. Change SPI write format 6. Modify SD card driver due to SPI write format changed 7. Modify building scripts git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1883 bbd45198-f89e-11dd-88c7-29a3b14d5316
206 lines
6.9 KiB
C
206 lines
6.9 KiB
C
/***************************************************************************//**
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* @file
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* @brief Watchdog (WDOG) peripheral API for EFM32
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* devices.
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* @author Energy Micro AS
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* @version 2.3.2
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*******************************************************************************
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* @section License
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* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
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*******************************************************************************
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*
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* This source code is the property of Energy Micro AS. The source and compiled
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* code may only be used on Energy Micro "EFM32" microcontrollers.
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*
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* This copyright notice may not be removed from the source code nor changed.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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******************************************************************************/
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#include "efm32_wdog.h"
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#include "efm32_bitband.h"
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/***************************************************************************//**
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* @addtogroup EFM32_Library
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @addtogroup WDOG
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* @brief Watchdog (WDOG) Peripheral API for EFM32
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* @{
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******************************************************************************/
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/*******************************************************************************
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************************** GLOBAL FUNCTIONS *******************************
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******************************************************************************/
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/***************************************************************************//**
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* @brief
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* Enable/disable the watchdog timer.
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*
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* @note
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* This function modifies the WDOG CTRL register which requires
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* synchronization into the low frequency domain. If this register is modified
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* before a previous update to the same register has completed, this function
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* will stall until the previous synchronization has completed.
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*
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* @param[in] enable
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* true to enable watchdog, false to disable. Watchdog cannot be disabled if
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* watchdog has been locked.
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******************************************************************************/
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void WDOG_Enable(bool enable)
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{
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if (!enable)
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{
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/* Wait for any pending previous write operation to have been completed in */
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/* low frequency domain */
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while (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
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;
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}
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BITBAND_Peripheral(&(WDOG->CTRL), _WDOG_CTRL_EN_SHIFT, (unsigned int)enable);
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}
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/***************************************************************************//**
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* @brief
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* Feed the watchdog.
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*
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* @details
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* When the watchdog is activated, it must be fed (ie clearing the counter)
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* before it reaches the defined timeout period. Otherwise, the watchdog
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* will generate a reset.
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******************************************************************************/
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void WDOG_Feed(void)
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{
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/* If a previous clearing is being synchronized to LF domain, then there */
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/* is no point in waiting for it to complete before clearing over again. */
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/* This avoids stalling the core in the typical use case where some idle loop */
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/* keeps clearing the watchdog. */
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if (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CMD)
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return;
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WDOG->CMD = WDOG_CMD_CLEAR;
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}
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/***************************************************************************//**
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* @brief
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* Initialize watchdog (assuming the watchdog configuration has not been
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* locked).
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*
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* @note
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* This function modifies the WDOG CTRL register which requires
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* synchronization into the low frequency domain. If this register is modified
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* before a previous update to the same register has completed, this function
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* will stall until the previous synchronization has completed.
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*
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* @param[in] init
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* Structure holding watchdog configuration. A default setting
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* #WDOG_INIT_DEFAULT is available for init.
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******************************************************************************/
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void WDOG_Init(const WDOG_Init_TypeDef *init)
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{
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uint32_t setting;
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if (init->enable)
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{
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setting = WDOG_CTRL_EN;
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}
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else
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{
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setting = 0;
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}
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if (init->debugRun)
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{
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setting |= WDOG_CTRL_DEBUGRUN;
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}
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if (init->em2Run)
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{
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setting |= WDOG_CTRL_EM2RUN;
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}
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if (init->em3Run)
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{
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setting |= WDOG_CTRL_EM3RUN;
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}
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if (init->em4Block)
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{
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setting |= WDOG_CTRL_EM4BLOCK;
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}
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if (init->swoscBlock)
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{
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setting |= WDOG_CTRL_SWOSCBLOCK;
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}
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setting |= ((uint32_t)(init->clkSel) << _WDOG_CTRL_CLKSEL_SHIFT) |
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((uint32_t)(init->perSel) << _WDOG_CTRL_PERSEL_SHIFT);
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/* Wait for any pending previous write operation to have been completed in */
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/* low frequency domain */
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while (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
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;
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WDOG->CTRL = setting;
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/* Optional register locking */
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if (init->lock)
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{
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if (init->enable)
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{
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WDOG_Lock();
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}
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else
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{
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BITBAND_Peripheral(&(WDOG->CTRL), _WDOG_CTRL_LOCK_SHIFT, 1);
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}
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}
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}
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/***************************************************************************//**
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* @brief
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* Lock the watchdog configuration.
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*
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* @details
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* This prevents errors from overwriting the watchdog configuration, possibly
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* disabling it. Only a reset can unlock the watchdog config, once locked.
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*
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* If the LFRCO or LFXO clocks are used to clock the watchdog, one should
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* consider using the option of inhibiting those clocks to be disabled,
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* please see the WDOG_Enable() init structure.
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*
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* @note
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* This function modifies the WDOG CTRL register which requires
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* synchronization into the low frequency domain. If this register is modified
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* before a previous update to the same register has completed, this function
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* will stall until the previous synchronization has completed.
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******************************************************************************/
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void WDOG_Lock(void)
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{
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/* Wait for any pending previous write operation to have been completed in */
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/* low frequency domain */
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while (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
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;
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/* Disable writing to the control register */
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BITBAND_Peripheral(&(WDOG->CTRL), _WDOG_CTRL_LOCK_SHIFT, 1);
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}
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/** @} (end addtogroup WDOG) */
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/** @} (end addtogroup EFM32_Library) */
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