714 lines
19 KiB
C
714 lines
19 KiB
C
/** @file esm.c
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* @brief Esm Driver Source File
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* @date 29.May.2013
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* @version 03.05.02
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*
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* This file contains:
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* - API Functions
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* .
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* which are relevant for the Esm driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Include Files */
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#include "esm.h"
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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/** @fn void esmInit(void)
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* @brief Initializes Esm Driver
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*
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* This function initializes the Esm driver.
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*
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*/
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/* USER CODE BEGIN (2) */
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/* USER CODE END */
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void esmInit(void)
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{
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/* USER CODE BEGIN (3) */
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/* USER CODE END */
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/** - Disable error pin channels */
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esmREG->EPENACLR1 = 0xFFFFFFFFU;
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esmREG->EPENACLR4 = 0xFFFFFFFFU;
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/** - Disable interrupts */
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esmREG->INTENACLR1 = 0xFFFFFFFFU;
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esmREG->INTENACLR4 = 0xFFFFFFFFU;
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/** - Clear error status flags */
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esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;
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esmREG->ESTATUS1[1U] = 0xFFFFFFFFU;
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esmREG->ESTATUS2EMU = 0xFFFFFFFFU;
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esmREG->ESTATUS1[2U] = 0xFFFFFFFFU;
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esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;
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esmREG->ESTATUS4[1U] = 0xFFFFFFFFU;
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esmREG->ESTATUS5EMU = 0xFFFFFFFFU;
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esmREG->ESTATUS4[2U] = 0xFFFFFFFFU;
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/** - Setup LPC preload */
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esmREG->LTCPRELOAD = 16384U - 1U;
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/** - Reset error pin */
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if (esmREG->EPSTATUS == 0U)
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{
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esmREG->KEY = 0x00000005U;
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}
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else
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{
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esmREG->KEY = 0x00000000U;
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}
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/** - Clear interrupt level */
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esmREG->INTLVLCLR1 = 0xFFFFFFFFU;
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esmREG->INTLVLCLR4 = 0xFFFFFFFFU;
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/** - Set interrupt level */
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esmREG->INTLVLSET1 = (0U << 31U)
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| (0U << 30U)
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| (0U << 29U)
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| (0U << 28U)
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| (0U << 27U)
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| (0U << 26U)
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| (0U << 25U)
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| (0U << 24U)
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| (0U << 23U)
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| (0U << 22U)
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| (0U << 21U)
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| (0U << 20U)
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| (0U << 19U)
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| (0U << 18U)
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| (0U << 17U)
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| (0U << 16U)
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| (0U << 15U)
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| (0U << 14U)
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| (0U << 13U)
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| (0U << 12U)
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| (0U << 11U)
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| (0U << 10U)
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| (0U << 9U)
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| (0U << 8U)
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| (0U << 7U)
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| (0U << 6U)
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| (0U << 5U)
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| (0U << 4U)
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| (0U << 3U)
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| (0U << 2U)
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| (0U << 1U)
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| (0U);
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esmREG->INTLVLSET4 = (0U << 31U)
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| (0U << 30U)
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| (0U << 29U)
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| (0U << 28U)
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| (0U << 27U)
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| (0U << 26U)
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| (0U << 25U)
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| (0U << 24U)
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| (0U << 23U)
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| (0U << 22U)
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| (0U << 21U)
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| (0U << 20U)
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| (0U << 19U)
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| (0U << 18U)
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| (0U << 17U)
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| (0U << 16U)
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| (0U << 15U)
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| (0U << 14U)
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| (0U << 13U)
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| (0U << 12U)
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| (0U << 11U)
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| (0U << 10U)
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| (0U << 9U)
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| (0U << 8U)
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| (0U << 7U)
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| (0U << 6U)
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| (0U << 5U)
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| (0U << 4U)
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| (0U << 3U)
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| (0U << 2U)
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| (0U << 1U)
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| (0U);
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/** - Enable error pin channels */
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esmREG->EPENASET1 = (0U << 31U)
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| (0U << 30U)
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| (0U << 29U)
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| (0U << 28U)
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| (0U << 27U)
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| (0U << 26U)
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| (0U << 25U)
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| (0U << 24U)
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| (0U << 23U)
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| (0U << 22U)
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| (0U << 21U)
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| (0U << 20U)
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| (0U << 19U)
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| (0U << 18U)
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| (0U << 17U)
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| (0U << 16U)
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| (0U << 15U)
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| (0U << 14U)
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| (0U << 13U)
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| (0U << 12U)
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| (0U << 11U)
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| (0U << 10U)
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| (0U << 9U)
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| (0U << 8U)
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| (0U << 7U)
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| (0U << 6U)
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| (0U << 5U)
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| (0U << 4U)
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| (0U << 3U)
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| (0U << 2U)
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| (0U << 1U)
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| (0U);
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esmREG->EPENASET4 = (0U << 31U)
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| (0U << 30U)
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| (0U << 29U)
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| (0U << 28U)
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| (0U << 27U)
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| (0U << 26U)
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| (0U << 25U)
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| (0U << 24U)
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| (0U << 23U)
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| (0U << 22U)
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| (0U << 21U)
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| (0U << 20U)
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| (0U << 19U)
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| (0U << 18U)
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| (0U << 17U)
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| (0U << 16U)
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| (0U << 15U)
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| (0U << 14U)
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| (0U << 13U)
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| (0U << 12U)
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| (0U << 11U)
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| (0U << 10U)
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| (0U << 9U)
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| (0U << 8U)
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| (0U << 7U)
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| (0U << 6U)
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| (0U << 5U)
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| (0U << 4U)
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| (0U << 3U)
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| (0U << 2U)
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| (0U << 1U)
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| (0U);
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/** - Enable interrupts */
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esmREG->INTENASET1 = (0U << 31U)
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| (0U << 30U)
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| (0U << 29U)
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| (0U << 28U)
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| (0U << 27U)
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| (0U << 26U)
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| (0U << 25U)
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| (0U << 24U)
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| (0U << 23U)
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| (0U << 22U)
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| (0U << 21U)
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| (0U << 20U)
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| (0U << 19U)
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| (0U << 18U)
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| (0U << 17U)
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| (0U << 16U)
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| (0U << 15U)
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| (0U << 14U)
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| (0U << 13U)
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| (0U << 12U)
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| (0U << 11U)
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| (0U << 10U)
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| (0U << 9U)
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| (0U << 8U)
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| (0U << 7U)
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| (0U << 6U)
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| (0U << 5U)
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| (0U << 4U)
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| (0U << 3U)
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| (0U << 2U)
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| (0U << 1U)
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| (0U);
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esmREG->INTENASET4 = (0U << 31U)
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| (0U << 30U)
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| (0U << 29U)
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| (0U << 28U)
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| (0U << 27U)
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| (0U << 26U)
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| (0U << 25U)
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| (0U << 24U)
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| (0U << 23U)
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| (0U << 22U)
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| (0U << 21U)
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| (0U << 20U)
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| (0U << 19U)
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| (0U << 18U)
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| (0U << 17U)
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| (0U << 16U)
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| (0U << 15U)
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| (0U << 14U)
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| (0U << 13U)
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| (0U << 12U)
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| (0U << 11U)
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| (0U << 10U)
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| (0U << 9U)
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| (0U << 8U)
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| (0U << 7U)
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| (0U << 6U)
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| (0U << 5U)
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| (0U << 4U)
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| (0U << 3U)
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| (0U << 2U)
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| (0U << 1U)
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| (0U);
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/* USER CODE BEGIN (4) */
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/* USER CODE END */
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}
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/** @fn uint32 esmError(void)
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* @brief Return Error status
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*
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* @return The error status
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*
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* Returns the error status.
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*/
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uint32 esmError(void)
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{
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uint32 status;
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/* USER CODE BEGIN (5) */
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/* USER CODE END */
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status = esmREG->EPSTATUS;
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/* USER CODE BEGIN (6) */
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/* USER CODE END */
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return status;
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}
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/** @fn void esmEnableError(uint64 channels)
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* @brief Enable Group 1 Channels Error Signals propagation
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*
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* @param[in] channels - Channel mask
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*
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* Enable Group 1 Channels Error Signals propagation to the error pin.
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*/
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void esmEnableError(uint64 channels)
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{
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/* USER CODE BEGIN (7) */
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/* USER CODE END */
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esmREG->EPENASET4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
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esmREG->EPENASET1 = (uint32)(channels & 0xFFFFFFFFU);
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/* USER CODE BEGIN (8) */
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/* USER CODE END */
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}
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/** @fn void esmDisableError(uint64 channels)
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* @brief Disable Group 1 Channels Error Signals propagation
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*
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* @param[in] channels - Channel mask
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*
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* Disable Group 1 Channels Error Signals propagation to the error pin.
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*/
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void esmDisableError(uint64 channels)
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{
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/* USER CODE BEGIN (9) */
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/* USER CODE END */
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esmREG->EPENACLR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
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esmREG->EPENACLR1 = (uint32)(channels & 0xFFFFFFFFU);
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/* USER CODE BEGIN (10) */
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/* USER CODE END */
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}
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/** @fn void esmTriggerErrorPinReset(void)
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* @brief Trigger error pin reset and switch back to normal operation
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*
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* Trigger error pin reset and switch back to normal operation.
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*/
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void esmTriggerErrorPinReset(void)
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{
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/* USER CODE BEGIN (11) */
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/* USER CODE END */
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esmREG->KEY = 5U;
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/* USER CODE BEGIN (12) */
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/* USER CODE END */
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}
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/** @fn void esmActivateNormalOperation(void)
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* @brief Activate normal operation
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*
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* Activates normal operation mode.
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*/
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void esmActivateNormalOperation(void)
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{
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/* USER CODE BEGIN (13) */
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/* USER CODE END */
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esmREG->KEY = 0U;
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/* USER CODE BEGIN (14) */
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/* USER CODE END */
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}
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/** @fn void esmEnableInterrupt(uint64 channels)
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* @brief Enable Group 1 Channels Interrupts
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*
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* @param[in] channels - Channel mask
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*
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* Enable Group 1 Channels Interrupts.
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*/
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void esmEnableInterrupt(uint64 channels)
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{
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/* USER CODE BEGIN (15) */
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/* USER CODE END */
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esmREG->INTENASET4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
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esmREG->INTENASET1 = (uint32)(channels & 0xFFFFFFFFU);
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/* USER CODE BEGIN (16) */
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/* USER CODE END */
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}
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/** @fn void esmDisableInterrupt(uint64 channels)
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* @brief Disable Group 1 Channels Interrupts
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*
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* @param[in] channels - Channel mask
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*
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* Disable Group 1 Channels Interrupts.
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*/
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void esmDisableInterrupt(uint64 channels)
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{
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/* USER CODE BEGIN (17) */
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/* USER CODE END */
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esmREG->INTENACLR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
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esmREG->INTENACLR1 = (uint32)(channels & 0xFFFFFFFFU);
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/* USER CODE BEGIN (18) */
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/* USER CODE END */
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}
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/** @fn void esmSetInterruptLevel(uint64 channels, uint64 flags)
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* @brief Set Group 1 Channels Interrupt Levels
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*
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* @param[in] channels - Channel mask
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* @param[in] flags - Level mask: - 0: Low priority interrupt
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* - 1: High priority interrupt
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*
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* Set Group 1 Channels Interrupts levels.
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*/
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void esmSetInterruptLevel(uint64 channels, uint64 flags)
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{
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/* USER CODE BEGIN (19) */
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/* USER CODE END */
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esmREG->INTLVLCLR4 = (uint32)(((channels & (~flags)) >> 32U) & 0xFFFFFFFU);
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esmREG->INTLVLSET4 = (uint32)(((channels & flags) >> 32U) & 0xFFFFFFFFU);
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esmREG->INTLVLCLR1 = (uint32)((channels & (~flags)) & 0xFFFFFFFU);
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esmREG->INTLVLSET1 = (uint32)((channels & flags) & 0xFFFFFFFFU);
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/* USER CODE BEGIN (20) */
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/* USER CODE END */
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}
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/** @fn void esmClearStatus(uint32 group, uint64 channels)
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* @brief Clear Group error status
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*
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* @param[in] group - Error group
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* @param[in] channels - Channel mask
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*
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* Clear Group error status.
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*/
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void esmClearStatus(uint32 group, uint64 channels)
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{
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/* USER CODE BEGIN (21) */
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/* USER CODE END */
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esmREG->ESTATUS4[group] = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
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esmREG->ESTATUS1[group] = (uint32)(channels & 0xFFFFFFFFU);
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/* USER CODE BEGIN (22) */
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/* USER CODE END */
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}
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/** @fn void esmClearStatusBuffer(uint64 channels)
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* @brief Clear Group 2 error status buffer
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*
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* @param[in] channels - Channel mask
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*
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* Clear Group 2 error status buffer.
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*/
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void esmClearStatusBuffer(uint64 channels)
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{
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/* USER CODE BEGIN (23) */
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/* USER CODE END */
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esmREG->ESTATUS5EMU = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
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esmREG->ESTATUS2EMU = (uint32)(channels & 0xFFFFFFFFU);
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/* USER CODE BEGIN (24) */
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/* USER CODE END */
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}
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/** @fn void esmSetCounterPreloadValue(uint32 value)
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* @brief Set counter preload value
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*
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* @param[in] value - Counter preload value
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*
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* Set counter preload value.
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*/
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void esmSetCounterPreloadValue(uint32 value)
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{
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/* USER CODE BEGIN (25) */
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/* USER CODE END */
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esmREG->LTCPRELOAD = value & 0xC000U;
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/* USER CODE BEGIN (26) */
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/* USER CODE END */
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}
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/** @fn uint64 esmGetStatus(uint32 group, uint64 channels)
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* @brief Return Error status
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*
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* @param[in] group - Error group
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* @param[in] channels - Error Channels
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*
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* @return The channels status of selected group
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*
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* Returns the channels status of selected group.
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*/
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uint64 esmGetStatus(uint32 group, uint64 channels)
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{
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uint64 status;
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/* USER CODE BEGIN (27) */
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/* USER CODE END */
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/*SAFETYMCUSW 51 S MR:12.3 <REVIEWED> "Needs shifting for 64-bit value" */
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status = (((uint64)esmREG->ESTATUS4[group] << 32U) | (uint64)esmREG->ESTATUS1[group]) & channels;
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/* USER CODE BEGIN (28) */
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/* USER CODE END */
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return status;
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}
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/** @fn uint64 esmGetStatusBuffer(uint64 channels)
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* @brief Return Group 2 channel x Error status buffer
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*
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* @param[in] channels - Error Channels
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*
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* @return The channels status
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*
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* Returns the group 2 buffered status of selected channels.
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*/
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uint64 esmGetStatusBuffer(uint64 channels)
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{
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uint64 status;
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/* USER CODE BEGIN (29) */
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/* USER CODE END */
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/*SAFETYMCUSW 51 S MR:12.3 <REVIEWED> "Needs shifting for 64-bit value" */
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status = (((uint64)esmREG->ESTATUS5EMU << 32U) | (uint64)esmREG->ESTATUS2EMU) & channels;
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/* USER CODE BEGIN (30) */
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/* USER CODE END */
|
|
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return status;
|
|
}
|
|
|
|
/** @fn esmSelfTestFlag_t esmEnterSelfTest(void)
|
|
* @brief Return ESM Self test status
|
|
*
|
|
* @return ESM Self test status
|
|
*
|
|
* Returns the ESM Self test status.
|
|
*/
|
|
esmSelfTestFlag_t esmEnterSelfTest(void)
|
|
{
|
|
esmSelfTestFlag_t status;
|
|
|
|
/* USER CODE BEGIN (31) */
|
|
/* USER CODE END */
|
|
|
|
if(((esmREG->EPSTATUS & 0x1U) == 0x0U) && (esmREG->KEY == 0x0U))
|
|
{
|
|
status = esmSelfTest_NotStarted;
|
|
}
|
|
else
|
|
{
|
|
esmREG->KEY = 0xAU;
|
|
status = esmSelfTest_Active;
|
|
if((esmREG->EPSTATUS & 0x1U) != 0x0U)
|
|
{
|
|
status = esmSelfTest_Failed;
|
|
}
|
|
esmREG->KEY = 0x5U;
|
|
}
|
|
|
|
/* USER CODE BEGIN (32) */
|
|
/* USER CODE END */
|
|
|
|
return status;
|
|
}
|
|
|
|
/** @fn esmSelfTestFlag_t esmSelfTestStatus(void)
|
|
* @brief Return ESM Self test status
|
|
*
|
|
* Returns the ESM Self test status.
|
|
*/
|
|
esmSelfTestFlag_t esmSelfTestStatus(void)
|
|
{
|
|
esmSelfTestFlag_t status;
|
|
|
|
/* USER CODE BEGIN (33) */
|
|
/* USER CODE END */
|
|
|
|
if((esmREG->EPSTATUS & 0x1U) == 0x0U)
|
|
{
|
|
if(esmREG->KEY == 0x5U)
|
|
{
|
|
status = esmSelfTest_Active;
|
|
}
|
|
else
|
|
{
|
|
status = esmSelfTest_Failed;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = esmSelfTest_Passed;
|
|
}
|
|
|
|
/* USER CODE BEGIN (34) */
|
|
/* USER CODE END */
|
|
|
|
return status;
|
|
}
|
|
|
|
/** @fn void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type)
|
|
* @brief Get the initial or current values of the configuration registers
|
|
*
|
|
* @param[in] *config_reg: pointer to the struct to which the initial or current
|
|
* value of the configuration registers need to be stored
|
|
* @param[in] type: whether initial or current value of the configuration registers need to be stored
|
|
* - InitialValue: initial value of the configuration registers will be stored
|
|
* in the struct pointed by config_reg
|
|
* - CurrentValue: initial value of the configuration registers will be stored
|
|
* in the struct pointed by config_reg
|
|
*
|
|
* This function will copy the initial or current value (depending on the parameter 'type')
|
|
* of the configuration registers to the struct pointed by config_reg
|
|
*
|
|
*/
|
|
|
|
void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type)
|
|
{
|
|
if (type == InitialValue)
|
|
{
|
|
config_reg->CONFIG_EPENASET1 = ESM_EPENASET1_CONFIGVALUE;
|
|
config_reg->CONFIG_INTENASET1 = ESM_INTENASET1_CONFIGVALUE;
|
|
config_reg->CONFIG_INTLVLSET1 = ESM_INTLVLSET1_CONFIGVALUE;
|
|
config_reg->CONFIG_LTCPRELOAD = ESM_LTCPRELOAD_CONFIGVALUE;
|
|
config_reg->CONFIG_KEY = ESM_KEY_CONFIGVALUE;
|
|
config_reg->CONFIG_EPENASET4 = ESM_EPENASET4_CONFIGVALUE;
|
|
config_reg->CONFIG_INTENASET4 = ESM_INTENASET4_CONFIGVALUE;
|
|
config_reg->CONFIG_INTLVLSET4 = ESM_INTLVLSET4_CONFIGVALUE;
|
|
}
|
|
else
|
|
{
|
|
config_reg->CONFIG_EPENASET1 = esmREG->EPENASET1;
|
|
config_reg->CONFIG_INTENASET1 = esmREG->INTENASET1;
|
|
config_reg->CONFIG_INTLVLSET1 = esmREG->INTLVLSET1;
|
|
config_reg->CONFIG_LTCPRELOAD = esmREG->LTCPRELOAD;
|
|
config_reg->CONFIG_KEY = esmREG->KEY;
|
|
config_reg->CONFIG_EPENASET4 = esmREG->EPENASET4;
|
|
config_reg->CONFIG_INTENASET4 = esmREG->INTENASET4;
|
|
config_reg->CONFIG_INTLVLSET4 = esmREG->INTLVLSET4;
|
|
}
|
|
}
|
|
|
|
/* USER CODE BEGIN (35) */
|
|
/* USER CODE END */
|
|
|
|
/** @fn void esmHighInterrupt(void)
|
|
* @brief High Level Interrupt for ESM
|
|
*/
|
|
#pragma CODE_STATE(esmHighInterrupt, 32)
|
|
#pragma INTERRUPT(esmHighInterrupt, FIQ)
|
|
|
|
void esmHighInterrupt(void)
|
|
{
|
|
sint32 vec = esmREG->INTOFFH - 1U;
|
|
|
|
/* USER CODE BEGIN (36) */
|
|
/* USER CODE END */
|
|
|
|
if (vec >= 96U)
|
|
{
|
|
esmREG->ESTATUS4[1U] = 1U << (vec-96U);
|
|
esmGroup2Notification(vec-64U);
|
|
}
|
|
else if (vec >= 64U)
|
|
{
|
|
esmREG->ESTATUS4[0U] = 1U << (vec-64U);
|
|
esmGroup1Notification(vec-32U);
|
|
}
|
|
else if (vec >= 32U)
|
|
{
|
|
esmREG->ESTATUS1[1U] = 1U << (vec-32U);
|
|
esmGroup2Notification(vec-32U);
|
|
}
|
|
else if (vec >= 0U)
|
|
{
|
|
esmREG->ESTATUS1[0U] = 1U << vec;
|
|
esmGroup1Notification(vec);
|
|
}
|
|
else
|
|
{
|
|
esmREG->ESTATUS4[1U] = 0xFFFFFFFFU;
|
|
esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;
|
|
esmREG->ESTATUS1[1U] = 0xFFFFFFFFU;
|
|
esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;
|
|
}
|
|
|
|
/* USER CODE BEGIN (37) */
|
|
/* USER CODE END */
|
|
}
|
|
|
|
|
|
/* USER CODE BEGIN (41) */
|
|
/* USER CODE END */
|