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ea6d73f140
1. Upgrade Cortex driver library (CMSIS -> CMSIS & Device): version 2.3.2 -> 3.0.1 & 3.0.0 - Remove "bsp/efm32/Libraries/CMSIS/Lib/ARM", "bsp/efm32/Libraries/CMSIS/Lib/G++" and "bsp/efm32/Libraries/CMSIS/SVD" to save space 2. Upgrade EFM32 driver libraries (efm32lib -> emlib): version 2.3.2 -> 3.0.0 - Remove "bsp/efm32/Libraries/Device/EnergyMicro/EFM32LG" and "bsp/efm32/Libraries/Device/EnergyMicro/EFM32TG" to save space 3. Upgrade EFM32GG_DK3750 development kit driver library: version 1.2.2 -> 2.0.1 4. Upgrade EFM32_Gxxx_DK development kit driver library: version 1.7.3 -> 2.0.1 5. Add energy management unit driver and test code 6. Modify linker script and related code to compatible with new version of libraries 7. Change EFM32 branch version number to 1.0 8. Add photo frame demo application git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2122 bbd45198-f89e-11dd-88c7-29a3b14d5316
232 lines
22 KiB
C
232 lines
22 KiB
C
/**************************************************************************//**
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* @file
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* @brief efm32g_ebi Register and Bit Field definitions
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* @author Energy Micro AS
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* @version 3.0.0
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******************************************************************************
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* @section License
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* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
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******************************************************************************
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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*****************************************************************************/
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/**************************************************************************//**
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* @defgroup EFM32G_EBI
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* @{
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* @brief EFM32G_EBI Register Declaration
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*****************************************************************************/
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typedef struct
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{
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__IO uint32_t CTRL; /**< Control Register */
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__IO uint32_t ADDRTIMING; /**< Address Timing Register */
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__IO uint32_t RDTIMING; /**< Read Timing Register */
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__IO uint32_t WRTIMING; /**< Write Timing Register */
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__IO uint32_t POLARITY; /**< Polarity Register */
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__IO uint32_t ROUTE; /**< I/O Routing Register */
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} EBI_TypeDef; /** @} */
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/**************************************************************************//**
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* @defgroup EFM32G_EBI_BitFields
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* @{
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*****************************************************************************/
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/* Bit fields for EBI CTRL */
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#define _EBI_CTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_CTRL */
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#define _EBI_CTRL_MASK 0x00030F03UL /**< Mask for EBI_CTRL */
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#define _EBI_CTRL_MODE_SHIFT 0 /**< Shift value for EBI_MODE */
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#define _EBI_CTRL_MODE_MASK 0x3UL /**< Bit mask for EBI_MODE */
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#define _EBI_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
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#define _EBI_CTRL_MODE_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */
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#define _EBI_CTRL_MODE_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */
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#define _EBI_CTRL_MODE_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */
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#define EBI_CTRL_MODE_DEFAULT (_EBI_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_CTRL */
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#define EBI_CTRL_MODE_D8A8 (_EBI_CTRL_MODE_D8A8 << 0) /**< Shifted mode D8A8 for EBI_CTRL */
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#define EBI_CTRL_MODE_D16A16ALE (_EBI_CTRL_MODE_D16A16ALE << 0) /**< Shifted mode D16A16ALE for EBI_CTRL */
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#define EBI_CTRL_MODE_D8A24ALE (_EBI_CTRL_MODE_D8A24ALE << 0) /**< Shifted mode D8A24ALE for EBI_CTRL */
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#define EBI_CTRL_BANK0EN (0x1UL << 8) /**< Bank 0 Enable */
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#define _EBI_CTRL_BANK0EN_SHIFT 8 /**< Shift value for EBI_BANK0EN */
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#define _EBI_CTRL_BANK0EN_MASK 0x100UL /**< Bit mask for EBI_BANK0EN */
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#define _EBI_CTRL_BANK0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
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#define EBI_CTRL_BANK0EN_DEFAULT (_EBI_CTRL_BANK0EN_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_CTRL */
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#define EBI_CTRL_BANK1EN (0x1UL << 9) /**< Bank 1 Enable */
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#define _EBI_CTRL_BANK1EN_SHIFT 9 /**< Shift value for EBI_BANK1EN */
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#define _EBI_CTRL_BANK1EN_MASK 0x200UL /**< Bit mask for EBI_BANK1EN */
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#define _EBI_CTRL_BANK1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
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#define EBI_CTRL_BANK1EN_DEFAULT (_EBI_CTRL_BANK1EN_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_CTRL */
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#define EBI_CTRL_BANK2EN (0x1UL << 10) /**< Bank 2 Enable */
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#define _EBI_CTRL_BANK2EN_SHIFT 10 /**< Shift value for EBI_BANK2EN */
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#define _EBI_CTRL_BANK2EN_MASK 0x400UL /**< Bit mask for EBI_BANK2EN */
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#define _EBI_CTRL_BANK2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
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#define EBI_CTRL_BANK2EN_DEFAULT (_EBI_CTRL_BANK2EN_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_CTRL */
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#define EBI_CTRL_BANK3EN (0x1UL << 11) /**< Bank 3 Enable */
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#define _EBI_CTRL_BANK3EN_SHIFT 11 /**< Shift value for EBI_BANK3EN */
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#define _EBI_CTRL_BANK3EN_MASK 0x800UL /**< Bit mask for EBI_BANK3EN */
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#define _EBI_CTRL_BANK3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
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#define EBI_CTRL_BANK3EN_DEFAULT (_EBI_CTRL_BANK3EN_DEFAULT << 11) /**< Shifted mode DEFAULT for EBI_CTRL */
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#define EBI_CTRL_ARDYEN (0x1UL << 16) /**< ARDY Enable */
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#define _EBI_CTRL_ARDYEN_SHIFT 16 /**< Shift value for EBI_ARDYEN */
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#define _EBI_CTRL_ARDYEN_MASK 0x10000UL /**< Bit mask for EBI_ARDYEN */
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#define _EBI_CTRL_ARDYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
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#define EBI_CTRL_ARDYEN_DEFAULT (_EBI_CTRL_ARDYEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_CTRL */
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#define EBI_CTRL_ARDYTODIS (0x1UL << 17) /**< ARDY Timeout Disable */
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#define _EBI_CTRL_ARDYTODIS_SHIFT 17 /**< Shift value for EBI_ARDYTODIS */
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#define _EBI_CTRL_ARDYTODIS_MASK 0x20000UL /**< Bit mask for EBI_ARDYTODIS */
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#define _EBI_CTRL_ARDYTODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
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#define EBI_CTRL_ARDYTODIS_DEFAULT (_EBI_CTRL_ARDYTODIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EBI_CTRL */
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/* Bit fields for EBI ADDRTIMING */
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#define _EBI_ADDRTIMING_RESETVALUE 0x00000100UL /**< Default value for EBI_ADDRTIMING */
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#define _EBI_ADDRTIMING_MASK 0x00000303UL /**< Mask for EBI_ADDRTIMING */
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#define _EBI_ADDRTIMING_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */
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#define _EBI_ADDRTIMING_ADDRSETUP_MASK 0x3UL /**< Bit mask for EBI_ADDRSETUP */
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#define _EBI_ADDRTIMING_ADDRSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING */
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#define EBI_ADDRTIMING_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */
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#define _EBI_ADDRTIMING_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */
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#define _EBI_ADDRTIMING_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */
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#define _EBI_ADDRTIMING_ADDRHOLD_DEFAULT 0x00000001UL /**< Mode DEFAULT for EBI_ADDRTIMING */
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#define EBI_ADDRTIMING_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */
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/* Bit fields for EBI RDTIMING */
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#define _EBI_RDTIMING_RESETVALUE 0x00000000UL /**< Default value for EBI_RDTIMING */
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#define _EBI_RDTIMING_MASK 0x00030F03UL /**< Mask for EBI_RDTIMING */
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#define _EBI_RDTIMING_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */
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#define _EBI_RDTIMING_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */
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#define _EBI_RDTIMING_RDSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */
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#define EBI_RDTIMING_RDSETUP_DEFAULT (_EBI_RDTIMING_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING */
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#define _EBI_RDTIMING_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */
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#define _EBI_RDTIMING_RDSTRB_MASK 0xF00UL /**< Bit mask for EBI_RDSTRB */
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#define _EBI_RDTIMING_RDSTRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */
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#define EBI_RDTIMING_RDSTRB_DEFAULT (_EBI_RDTIMING_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING */
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#define _EBI_RDTIMING_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */
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#define _EBI_RDTIMING_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */
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#define _EBI_RDTIMING_RDHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */
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#define EBI_RDTIMING_RDHOLD_DEFAULT (_EBI_RDTIMING_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING */
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/* Bit fields for EBI WRTIMING */
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#define _EBI_WRTIMING_RESETVALUE 0x00010000UL /**< Default value for EBI_WRTIMING */
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#define _EBI_WRTIMING_MASK 0x00030F03UL /**< Mask for EBI_WRTIMING */
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#define _EBI_WRTIMING_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */
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#define _EBI_WRTIMING_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */
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#define _EBI_WRTIMING_WRSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */
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#define EBI_WRTIMING_WRSETUP_DEFAULT (_EBI_WRTIMING_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING */
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#define _EBI_WRTIMING_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */
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#define _EBI_WRTIMING_WRSTRB_MASK 0xF00UL /**< Bit mask for EBI_WRSTRB */
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#define _EBI_WRTIMING_WRSTRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */
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#define EBI_WRTIMING_WRSTRB_DEFAULT (_EBI_WRTIMING_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING */
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#define _EBI_WRTIMING_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */
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#define _EBI_WRTIMING_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */
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#define _EBI_WRTIMING_WRHOLD_DEFAULT 0x00000001UL /**< Mode DEFAULT for EBI_WRTIMING */
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#define EBI_WRTIMING_WRHOLD_DEFAULT (_EBI_WRTIMING_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING */
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/* Bit fields for EBI POLARITY */
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#define _EBI_POLARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY */
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#define _EBI_POLARITY_MASK 0x0000001FUL /**< Mask for EBI_POLARITY */
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#define EBI_POLARITY_CSPOL (0x1UL << 0) /**< Chip Select Polarity */
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#define _EBI_POLARITY_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */
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#define _EBI_POLARITY_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */
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#define _EBI_POLARITY_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
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#define _EBI_POLARITY_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
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#define _EBI_POLARITY_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
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#define EBI_POLARITY_CSPOL_DEFAULT (_EBI_POLARITY_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY */
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#define EBI_POLARITY_CSPOL_ACTIVELOW (_EBI_POLARITY_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
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#define EBI_POLARITY_CSPOL_ACTIVEHIGH (_EBI_POLARITY_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
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#define EBI_POLARITY_REPOL (0x1UL << 1) /**< Read Enable Polarity */
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#define _EBI_POLARITY_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */
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#define _EBI_POLARITY_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */
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#define _EBI_POLARITY_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
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#define _EBI_POLARITY_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
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#define _EBI_POLARITY_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
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#define EBI_POLARITY_REPOL_DEFAULT (_EBI_POLARITY_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY */
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#define EBI_POLARITY_REPOL_ACTIVELOW (_EBI_POLARITY_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
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#define EBI_POLARITY_REPOL_ACTIVEHIGH (_EBI_POLARITY_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
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#define EBI_POLARITY_WEPOL (0x1UL << 2) /**< Write Enable Polarity */
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#define _EBI_POLARITY_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */
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#define _EBI_POLARITY_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */
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#define _EBI_POLARITY_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
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#define _EBI_POLARITY_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
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#define _EBI_POLARITY_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
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#define EBI_POLARITY_WEPOL_DEFAULT (_EBI_POLARITY_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY */
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#define EBI_POLARITY_WEPOL_ACTIVELOW (_EBI_POLARITY_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
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#define EBI_POLARITY_WEPOL_ACTIVEHIGH (_EBI_POLARITY_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
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#define EBI_POLARITY_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */
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#define _EBI_POLARITY_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */
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#define _EBI_POLARITY_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */
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#define _EBI_POLARITY_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
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#define _EBI_POLARITY_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
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#define _EBI_POLARITY_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
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#define EBI_POLARITY_ALEPOL_DEFAULT (_EBI_POLARITY_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY */
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#define EBI_POLARITY_ALEPOL_ACTIVELOW (_EBI_POLARITY_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
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#define EBI_POLARITY_ALEPOL_ACTIVEHIGH (_EBI_POLARITY_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
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#define EBI_POLARITY_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */
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#define _EBI_POLARITY_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */
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#define _EBI_POLARITY_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */
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#define _EBI_POLARITY_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
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#define _EBI_POLARITY_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
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#define _EBI_POLARITY_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
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#define EBI_POLARITY_ARDYPOL_DEFAULT (_EBI_POLARITY_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY */
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#define EBI_POLARITY_ARDYPOL_ACTIVELOW (_EBI_POLARITY_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
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#define EBI_POLARITY_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
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/* Bit fields for EBI ROUTE */
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#define _EBI_ROUTE_RESETVALUE 0x00000000UL /**< Default value for EBI_ROUTE */
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#define _EBI_ROUTE_MASK 0x0000007FUL /**< Mask for EBI_ROUTE */
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#define EBI_ROUTE_EBIPEN (0x1UL << 0) /**< EBI Pin Enable */
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#define _EBI_ROUTE_EBIPEN_SHIFT 0 /**< Shift value for EBI_EBIPEN */
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#define _EBI_ROUTE_EBIPEN_MASK 0x1UL /**< Bit mask for EBI_EBIPEN */
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#define _EBI_ROUTE_EBIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
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#define EBI_ROUTE_EBIPEN_DEFAULT (_EBI_ROUTE_EBIPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ROUTE */
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#define EBI_ROUTE_CS0PEN (0x1UL << 1) /**< EBI_CS0 Pin Enable */
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#define _EBI_ROUTE_CS0PEN_SHIFT 1 /**< Shift value for EBI_CS0PEN */
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#define _EBI_ROUTE_CS0PEN_MASK 0x2UL /**< Bit mask for EBI_CS0PEN */
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#define _EBI_ROUTE_CS0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
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#define EBI_ROUTE_CS0PEN_DEFAULT (_EBI_ROUTE_CS0PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_ROUTE */
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#define EBI_ROUTE_CS1PEN (0x1UL << 2) /**< EBI_CS1 Pin Enable */
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#define _EBI_ROUTE_CS1PEN_SHIFT 2 /**< Shift value for EBI_CS1PEN */
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#define _EBI_ROUTE_CS1PEN_MASK 0x4UL /**< Bit mask for EBI_CS1PEN */
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#define _EBI_ROUTE_CS1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
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#define EBI_ROUTE_CS1PEN_DEFAULT (_EBI_ROUTE_CS1PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_ROUTE */
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#define EBI_ROUTE_CS2PEN (0x1UL << 3) /**< EBI_CS2 Pin Enable */
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#define _EBI_ROUTE_CS2PEN_SHIFT 3 /**< Shift value for EBI_CS2PEN */
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#define _EBI_ROUTE_CS2PEN_MASK 0x8UL /**< Bit mask for EBI_CS2PEN */
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#define _EBI_ROUTE_CS2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
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#define EBI_ROUTE_CS2PEN_DEFAULT (_EBI_ROUTE_CS2PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_ROUTE */
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#define EBI_ROUTE_CS3PEN (0x1UL << 4) /**< EBI_CS3 Pin Enable */
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#define _EBI_ROUTE_CS3PEN_SHIFT 4 /**< Shift value for EBI_CS3PEN */
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#define _EBI_ROUTE_CS3PEN_MASK 0x10UL /**< Bit mask for EBI_CS3PEN */
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#define _EBI_ROUTE_CS3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
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#define EBI_ROUTE_CS3PEN_DEFAULT (_EBI_ROUTE_CS3PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_ROUTE */
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#define EBI_ROUTE_ALEPEN (0x1UL << 5) /**< EBI_ALE Pin Enable */
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#define _EBI_ROUTE_ALEPEN_SHIFT 5 /**< Shift value for EBI_ALEPEN */
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#define _EBI_ROUTE_ALEPEN_MASK 0x20UL /**< Bit mask for EBI_ALEPEN */
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#define _EBI_ROUTE_ALEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
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#define EBI_ROUTE_ALEPEN_DEFAULT (_EBI_ROUTE_ALEPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_ROUTE */
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#define EBI_ROUTE_ARDYPEN (0x1UL << 6) /**< EBI_ARDY Pin Enable */
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#define _EBI_ROUTE_ARDYPEN_SHIFT 6 /**< Shift value for EBI_ARDYPEN */
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#define _EBI_ROUTE_ARDYPEN_MASK 0x40UL /**< Bit mask for EBI_ARDYPEN */
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#define _EBI_ROUTE_ARDYPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
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#define EBI_ROUTE_ARDYPEN_DEFAULT (_EBI_ROUTE_ARDYPEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_ROUTE */
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/** @} End of group EFM32G_EBI */
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